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| Chair |
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Masahiko Yoshimoto (Kobe Univ.) |
| Vice Chair |
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Takeshi Yamamura (Fujitsu Labs.) |
| Secretary |
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Hiroaki Suzuki (Renesas), Toshimasa Matsuoka (Osaka Univ.) |
| Assistant |
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Ken Takeuchi (Univ. of Tokyo), Osamu Watanabe (Toshiba), Akira Tsuchiya (Kyoto Univ.) |
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| Conference Date |
Thu, Dec 15, 2011 10:30 - 18:20
Fri, Dec 16, 2011 09:55 - 16:40 |
| Topics |
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| Conference Place |
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| Sponsors |
This conference is co-sponsored by the IEEE-SSCS Japan/Kansai Chapter.
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Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, Dec 15 AM
10:30 - 11:45 |
| (1) |
10:30-10:55 |
An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS  ICD2011-100 |
Sang-Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech.) |
| (2) |
10:55-11:45 |
[Invited Talk]
Challenging of semiconductor capability for comfortable human life
-- Future engineers, what's the role and skill -- ICD2011-101 |
Kazutami Arimoto (Renesas Electronics) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Thu, Dec 15 PM
13:00 - 14:15 |
| (3) |
13:00-13:50 |
[Invited Talk]
Tamper LSI Design Methodology using Physical Unclonable Function ICD2011-102 |
Takeshi Fujino, Kota Furuhashi, Mitsuru Shiozaki (Ritsumeikan Univ.) |
| (4) |
13:50-14:15 |
A study of the simulation methodology to analyze DC-DC converter's characteristics in high-speed and precice without using SPICE circuit simulator ICD2011-103 |
Tatsuya Furukawa, Yuya Hirano, Yasuhiro Sugimoto (Chuo Univ.) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Thu, Dec 15 PM
14:25 - 15:15 |
| (5) |
14:25-15:15 |
[Invited Talk]
To be a worldwide researcher!
-- Challenges to DAC and ISSCC -- ICD2011-126 |
Shingo Takahashi (NEC) |
| |
15:15-15:25 |
Break ( 10 min. ) |
Thu, Dec 15 PM
15:25 - 16:00 |
| (6) |
15:25-16:00 |
|
| |
16:00-16:10 |
Break ( 10 min. ) |
Thu, Dec 15 PM
16:10 - 18:20 |
| (7) |
16:10-18:00 |
[Poster Presentation]
The design of TDC and ADPLL circuits considering metastable operations ICD2011-104 |
Yasuyuki Shimizu (Osaka Inst. Tech.), Giichi Sakemi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) |
| (8) |
16:10-18:00 |
[Poster Presentation]
Broadband Low Noise Amplifier Design in Scaled CMOS Technology ICD2011-105 |
Ben Patrick (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.) |
| (9) |
16:10-18:00 |
[Poster Presentation]
Analog Circuit Design in Scaled CMOS Technologies ICD2011-106 |
Ying Yang, Jingbo Shi, Ben Patrick, Takayuki Konishi (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.) |
| (10) |
16:10-18:00 |
[Poster Presentation]
A Implementation Technique of a Multibit Successive Approximation Register AD Converter ICD2011-107 |
Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) |
| (11) |
16:10-18:00 |
[Poster Presentation]
Low-Power High-Speed Rail-to-Rail Voltage Buffer for LCD Drivers ICD2011-108 |
Yousuke Tsukamoto, Cong-Kha Pham (UEC) |
| (12) |
16:10-18:00 |
[Poster Presentation]
Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits ICD2011-109 |
Yasushi Kishiwada, Shun Ueda, Yusuke Miyawaki, Toshimasa Matsuoka (Osaka Univ.) |
| (13) |
16:10-18:00 |
[Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits. ICD2011-110 |
Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) |
| (14) |
16:10-18:00 |
[Poster Presentation]
Comparator for A/D converter using time-to-digital converter ICD2011-111 |
Naoki Isobe, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.) |
| (15) |
16:10-18:00 |
[Poster Presentation]
Analysis of the Neural Spike Recording Amplifier with Telescopic OPA ICD2011-112 |
Chisato Takatsuki, Takeshi Yoshida (Hiroshima Univ.) |
| (16) |
16:10-18:00 |
[Poster Presentation]
Efficient Execution of Floating Point Instructions in CRIB ICD2011-113 |
Naoaki Ohkubo, Kenji Kise (TokyoTech) |
| (17) |
16:10-18:00 |
[Poster Presentation]
Sleep Depth Controlling for Run-Time Leakage Power Saving ICD2011-114 |
Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura (Tokyo Univ.) |
| (18) |
16:10-18:00 |
[Poster Presentation]
A study of a 1.5V operational cyclic current-mode ADC utilizing the pipeline conversion architecture ICD2011-115 |
Masatoshi Kamuro, Masanobu Ota, Yasuhiro Sugimoto (Chuo Univ.) |
| (19) |
16:10-18:00 |
[Poster Presentation]
Endurance enhancement programming method for 50nm resistive random access memory (ReRAM) ICD2011-116 |
Kazuhide Higuchi, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi (Univ. of Tokyo) |
| (20) |
16:10-18:00 |
[Poster Presentation]
4-Times Faster Rising Vpass (10V), 15% Lower Power Vpgm (20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives ICD2011-117 |
Teruyoshi Hatanaka, Ken Takeuchi (Tokyo Univ.) |
| (21) |
16:10-18:00 |
[Poster Presentation]
An oscillator-based true random number generator with jitter amplifier ICD2011-118 |
Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| (22) |
16:10-18:00 |
[Poster Presentation]
Estimation of Soft Error Rate on a Via Programmable Logic "VPEX" ICD2011-119 |
Taisuke Ueoka, Ryohei Hori, Tatsuya Kitamori (Ritsumeikan Univ), Masaya Yoshikawa (MeijoUniv), Takeshi Fujino (Ritsumeikan Univ) |
| (23) |
16:10-18:00 |
[Poster Presentation]
Via programmable analog circuit (VPA): New approach for analog circuits ICD2011-120 |
Ryo Nakazawa, Ryohei Hori, Keisuke Ueda, Mitsuru Shiozaki, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ) |
| (24) |
16:10-18:00 |
[Poster Presentation]
Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling ICD2011-121 |
Igors Homjakovs, Masanori Hashimoto (Osaka Univ.), Tetsuya Hirose (Kobe Univ.), Takao Onoye (Osaka Univ.) |
| (25) |
16:10-18:00 |
[Poster Presentation]
A Study on High Resolution SAR ADC ICD2011-122 |
Toyoki Asazawa, Yoshihiro Tsunokawa, Masaya Miyahara, Akira Matsuzawa (Titech) |
| (26) |
16:10-18:00 |
[Poster Presentation]
High Linearity Open-loop Amplifier for Interpolated Pipeline ADC ICD2011-123 |
Yoshiyuki Hirooka, Hyunui Lee, Masaya Miyahara, Akira Matsuzawa (Titech) |
| (27) |
16:10-18:00 |
[Poster Presentation]
A 60GHz CMOS Direct-conversion Transceiver ICD2011-124 |
Tatsuya Yamaguchi, Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Ryo Minami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa (Titech) |
| (28) |
16:10-18:00 |
[Poster Presentation]
Designing Technique of a Single-Differential LNA ICD2011-125 |
Takahiro Masumoto, Daisuke Kanemoto, Haruichi Kanaya (Kyushu Univ.), Ramesh Pokharel (E-JUST center), Keiji Yoshida (Kyushu Univ.) |
| (29) |
18:00-18:20 |
|
Fri, Dec 16 AM
09:55 - 10:20 |
| (30) |
09:55-10:20 |
A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets ICD2011-129 |
Ryosuke Yamamoto, Chikara Hamanaka (Kyoto Inst. of Tech.), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) |
| |
10:20-10:30 |
Break ( 10 min. ) |
Fri, Dec 16 AM
10:30 - 11:45 |
| (31) |
10:30-11:20 |
[Tutorial Lecture]
Technology Trends in ISSCC TD(Technology Direction) ICD2011-127 |
Masaitsu Nakajima (Panasonic Corp.) |
| (32) |
11:20-11:45 |
Hardware software co-design methodology tolerating software redundancy ICD2011-130 |
Yuta Teranishi (Fujitsu Qnet), Toshiya Otomo, Koji Kurihara, Hiromasa Yamauchi, Takahisa Suzuki, Koichiro Yamashita (Fujitsu Lab) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Fri, Dec 16 PM
13:00 - 14:15 |
| (33) |
13:00-13:50 |
[Invited Talk]
Ultra-Low Voltage and Extremely-Low Power Logic Circuit Design ICD2011-128 |
Hiroshi Fuketa (Univ. Tokyo) |
| (34) |
13:50-14:15 |
A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers ICD2011-132 |
Keisuke Okuno, Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) |
| |
14:15-14:25 |
Break ( 10 min. ) |
Fri, Dec 16 PM
14:25 - 15:15 |
| (35) |
14:25-14:50 |
0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation ICD2011-133 |
Shusuke Yoshimoto, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) |
| (36) |
14:50-15:15 |
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure ICD2011-134 |
Yohei Umeki, Shusuke Yoshimoto, Takurou Amashita, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST) |
| |
15:15-15:25 |
Break ( 10 min. ) |
Fri, Dec 16 PM
15:25 - 16:40 |
| (37) |
15:25-16:15 |
[Invited Talk]
Power Noise in VLSI Chip
-- from Silicon Substrate to Electromagnetic Environment -- ICD2011-131 |
Makoto Nagata (Kobe Univ.) |
| (38) |
16:15-16:40 |
A Study on Delta Modulation Domain A/D Circuit using EF Sub-ADC |
Kensuke Yamamoto, Naoki Koike, Takeshi Yoshida (Hiroshima Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Invited Talk | Each speech will have 40 minutes for presentation and 10 minutes for discussion. |
| Tutorial Lecture | Each speech will have 40 minutes for presentation and 10 minutes for discussion. |
| Poster Presentation | Each speech will have 110 minutes for presentation. |
| Contact Address and Latest Schedule Information |
| ICD |
Technical Committee on Integrated Circuits and Devices (ICD) [Latest Schedule]
|
| Contact Address |
Osamu Watanabe (Toshiba Corporation)
TEL 044-549-2283,FAX 044-520-1806
E- :o  7    be   ba |
Last modified: 2011-12-02 10:57:39
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