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| Chair |
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Hirofumi Hamamura |
| Vice Chair |
|
Nagisa Ishiura |
| Secretary |
|
Toshiyuki Shibuya, Hiroyuki Ochi |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
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| Conference Date |
Thu, May 10, 2007 13:30 - 17:00
Fri, May 11, 2007 09:30 - 15:00 |
| Topics |
System Design, etc. |
| Conference Place |
Kyodai Kaikan |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, May 10 PM Architecture
Chair: Kiyoharu Hamaguchi (Osaka Univ.)
13:30 - 14:45 |
| (1) |
13:30-13:55 |
Memory Assignment Method for Matrix Processing Array  VLD2007-1 |
Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) |
| (2) |
13:55-14:20 |
Heuristic Instruction Scheduling Method for Processors with Partial Data Forwarding Structure |
Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| (3) |
14:20-14:45 |
Reconfigurable Architecture with Caluculation Function for Shift Keying VLD2007-3 |
Ayataka Kobayashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| |
14:45-14:55 |
Break ( 10 min. ) |
Thu, May 10 PM
Chair: Tohru Ishihara (Kyushu Univ.)
14:55 - 15:45 |
| (4) |
14:55-15:20 |
A Modeling of Dynamically Reconfigurable Processor using SystemC |
Kouji Ueda, Junji Kitamichi, Kenichi Kuroda (The Univ. of Aidu) |
| (5) |
15:20-15:45 |
An Architecture Design and its Evaluation for Speech Recognition System VLD2007-5 |
Joh Hashimato, Makoto Saitsuji, Takashi Kambe (Kinki Univ.) |
| |
15:45-16:00 |
Break ( 15 min. ) |
Thu, May 10 PM
16:00 - 17:00 |
| (6) |
16:00-17:00 |
[Panel Discussion]
Highlevel synthesis; will it be useful or useless? VLD2007-6 |
Masahiro Fukui (Ritsumeikan Univ.), Nagisa Ishiura (Kwansei Gakuin Univ.), Tomonori Izumi (Ritsumeikan Univ.), Akihisa Yamada (SHARP) |
Fri, May 11 AM
09:30 - 10:45 |
| (7) |
09:30-09:55 |
Automatic Generation of a Verification Environment for Hardware Units
-- Application to a Bus Bridge Design -- VLD2007-7 |
Rafael Kazumiti Morizawa, Hiroaki Iwashita, Koichiro Takayama (Fujitsu Labs.) |
| (8) |
09:55-10:20 |
On a lower bound for DAG covering problem and its application to an exact algorithm VLD2007-8 |
Yusuke Matsunaga (Kyushu Univ.) |
| (9) |
10:20-10:45 |
A Clock Deskew Method using PDE with Discrete Delay VLD2007-9 |
Yuko Hashizume, Naoki Otani, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
| |
10:45-10:55 |
Break ( 10 min. ) |
Fri, May 11 AM
10:55 - 12:10 |
| (10) |
10:55-11:20 |
An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA VLD2007-10 |
Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) |
| (11) |
11:20-11:45 |
An SIMD MSD Multiplier based on variable GF($2^m$) for Elliptic Curve Cryptosystem VLD2007-11 |
Ryuta Nara, Kazunori Shimizu, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (12) |
11:45-12:10 |
On power-conscious approach for prefix graph synthesis |
Taeko Matsunaga (Waseda Univ), Yusuke Matsunaga (Kyushu Univ.) |
| |
12:10-13:20 |
Lunch Break ( 70 min. ) |
Fri, May 11 PM
13:20 - 15:00 |
| (13) |
13:20-13:45 |
A Flexible Power and Task Modeling for LSI Blocks |
Tatsuya Koyagi, Masahiro Fukui (Ritsumeikan Univ.), Resve Saleh (Univ. of British Columbia) |
| (14) |
13:45-14:10 |
A fast maximum delay estimation method for specified yield by statistical static timing analysis. VLD2007-14 |
Hiroki Furuya, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) |
| (15) |
14:10-14:35 |
An algorithm of power grid optimization for high-level floorplan |
Takayuki Hayashi, Yoshiyuki Kawakami, Masahiro Fukui (Ritsumeikan Univ.) |
| (16) |
14:35-15:00 |
Effect of Dummy Fill on High-Frequency Characteristics of On-Chip Interconnects VLD2007-16 |
Akira Tsuchiya, Hidetoshi Onodera (Kyoto Univ.) |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Shibuya Toshiyuki(Fujitsu Laboratories)
E- : bu      
Tel.044-754-2663 |
| Announcement |
You will see the latest information at the below WEB page.
http://www.ieice.org/~vld/ |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
|
Last modified: 2007-04-26 17:11:17
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