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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-02 12:05 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Study on formal verification of GF(2^m) arithmetic circuits including states Kazuho Sakoda (SCU/Kobe Univ.), Yasuyoshi Uemura (SCU), Naofumi Homma (Tohoku Univ.)  VLD2023-140 HWS2023-100 ICD2023-129 |
This paper describes a formal verification method for arithmetic circuits based on computer algebra. Conventional method... [more] | VLD2023-140 HWS2023-100 ICD2023-129 pp.215-220 |
| IT, ISEC, RCC, WBS | 2022-03-10 09:40 |
Online | Online | Construction GKW Transformation for Arithmetic Circuits Kotaro Chinen, Hiroaki Anada (Univ. Nagasaki) IT2021-88 ISEC2021-53 WBS2021-56 RCC2021-63 |
Garbled ciruits is a cryptographic framework for secure two-party computation introduced by Yao. Yao's protocol is a met... [more] | IT2021-88 ISEC2021-53 WBS2021-56 RCC2021-63 pp.31-37 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:30 |
Kanagawa | Hiyoshi Campus, Keio University | Error detection using residue signed-digit number arithmetic for arithmetic circuits Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) VLD2014-136 CPSY2014-145 RECONF2014-69 |
For error detection of multiply-accumulate operation, a residue error detector can be considered for the VLSI implementa... [more] | VLD2014-136 CPSY2014-145 RECONF2014-69 pp.151-156 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 11:15 |
Kanagawa | Hiyoshi Campus, Keio University | Error Checker using Binary tree structure of Residue Signed-Digit Additions Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) VLD2011-111 CPSY2011-74 RECONF2011-70 |
In this paper, a fast residue checker for error detection of arithmetic circuits is presented. The residue checker consi... [more] | VLD2011-111 CPSY2011-74 RECONF2011-70 pp.117-121 |
| RCS | 2011-06-24 17:00 |
Okinawa | Ryukyu Univ. | Calculation and Evaluation of MMSE weight matrix using Fixed-point Arithmetic Kazuhiko Mitsuyama (NHK/Keio Univ.), Tetsuomi Ikeda (NHK), Tomoaki Ohtsuki (Keio Univ.) RCS2011-74 |
We have been studying a macrodiversity system that can receive Hi-Vision (HDTV) videos across wide area without outage i... [more] | RCS2011-74 pp.227-232 |
| DC, CPSY | 2009-04-21 13:50 |
Tokyo | Akihabara Satellite Campus, Tokyo Metropolitan Univ. | Fast Soft Error Rate Estimation for Circuits Containing Arithmetic Units Motoharu Hirata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura (Kyushu Univ.) CPSY2009-5 DC2009-5 |
This paper describes soft errors which are errors in LSI that are due to external radiation.The soft error rate (SER) wh... [more] | CPSY2009-5 DC2009-5 pp.25-30 |
| RECONF | 2008-05-22 16:05 |
Fukushima | The University of Aizu | A Novel Cluster Structure for Variable Grain Logic Cell Kazuki Inoue, Kazunori Matsuyama, Yoshiaki Satou, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-8 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-8 pp.43-48 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 09:50 |
Kagoshima | An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA Masayuki Hiromoto, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.) DC2007-105 CPSY2007-101 |
Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-... [more] | DC2007-105 CPSY2007-101 pp.127-132 |
|
| RECONF | 2007-05-17 16:10 |
Ishikawa | Kanazawa Bunka Hall | Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2007-7 |
Reconfigurable logic devices are classified into two type of logic block, which are coarse-grain and fine-grain by the b... [more] | RECONF2007-7 pp.37-42 |
| RECONF | 2006-09-14 14:45 |
Kumamoto | Kumamoto Univ. | A logic design technique using SRAM blocks Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ) |
A low power on-board reconfigurable tester have been developed by using an FPGA. It is technically possible to configure... [more] | RECONF2006-23 pp.17-22 |
| NLP | 2006-05-11 14:25 |
Kumamoto | Kumamoto Univ. | Stochastic Computing with Quantization Noise Shaping Naoya Yamamoto, Hisato Fujisaka, Kazuhisa Haeiwa, Takeshi Kamio (Hiroshima City Univ.) |
This paper presents a bit-rate converter and arithmetic circuits for nanoelectronic signal processing systems based on s... [more] | NLP2006-5 pp.21-25 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 14:20 |
Fukuoka | Kitakyushu International Conference Center | Consideration on Delay Estimation Methods for Prefix Graphs Taeko Matsunaga (FLEETS), Yusuke Matsunaga (Kyushu Univ.) |
Prefix graph is an abstract representation of a parallel prefix adder and used to compare characteristics of various typ... [more] | VLD2005-69 ICD2005-164 DC2005-46 pp.49-54 |
| CAS, SIP, VLD | 2005-06-28 13:50 |
Miyagi | Tohoku University | Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH Yuki Watanabe, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohtech) |
This paper presents a design of parallel multipliers based on arithmetic description language called ARITH. The multipli... [more] | CAS2005-21 VLD2005-32 SIP2005-45 pp.37-42 |
| MSS, CAS | 2004-11-04 11:20 |
Aichi | Aichi Pref. Univ. | Arithmetic Cost Reduction Algorithm for Linear Transformation Circuits Considering the Synthesis Order of Coeficient Set Keisuke Sato, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) |
For synthesis of linear transformation circuits, it is generally used that the coefficient matrix is partitioned i... [more] |
CAS2004-46 CST2004-25 pp.25-28 |
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