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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2007)
Search Results: Keywords 'from:2008-03-05 to:2008-03-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, ICD | 2008-03-06 16:10 |
Okinawa | TiRuRu | Global Routing Method of Plating Lead for 2-Layer BGA Packages Naoki Sato, Yoichi Tomioka, Atsushi Takahashi (Tokyo Tech)  VLD2007-154 ICD2007-177 |
In this paper, we propose a global routing method for 2-layer BGA packages in which the layer assignment of plating le... [more] |
VLD2007-154 ICD2007-177 pp.61-66 |
| VLD, ICD | 2008-03-06 16:35 |
Okinawa | TiRuRu | Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178 |
Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] | VLD2007-155 ICD2007-178 pp.67-72 |
| VLD, ICD | 2008-03-07 09:15 |
Okinawa | TiRuRu | A delay balancing technique for wave-pipelining Keiichiro Sano, Jubee Tada (Yamagata Univ), Ryusuke Egawa (Touhoku Univ), Gensuke Goto (Yamagata Univ) VLD2007-156 ICD2007-179 |
Wave pipeline is a cutting-edge technology as an alternative to traditional pipeline, However, wave pipelining requires ... [more] | VLD2007-156 ICD2007-179 pp.1-6 |
| VLD, ICD | 2008-03-07 09:40 |
Okinawa | TiRuRu | Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) VLD2007-157 ICD2007-180 |
A multimedia mobile processor HCgorilla developed for ubiquitous network was built in Java CPU, cipher logic, and floati... [more] | VLD2007-157 ICD2007-180 pp.7-12 |
| VLD, ICD | 2008-03-07 10:05 |
Okinawa | TiRuRu | A Self-timed Processor with Dynamic Voltage Scaling Taku Sogabe, Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo) VLD2007-158 ICD2007-181 |
As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self... [more] | VLD2007-158 ICD2007-181 pp.13-18 |
| VLD, ICD | 2008-03-07 10:45 |
Okinawa | TiRuRu | A High-Throughput Architectures for LDPC Coded OFDM Baseband Processor Shinsuke Ushiki, Koichi Nakamura, Kazunori Shimizu, Qi Wang, Yuta Abe, Satoshi Goto, Takeshi Ikenaga (Waseda Univ.) VLD2007-159 ICD2007-182 |
It's research target more important that combined OFDM modulation with LDPC codes in digital wireless communication syst... [more] | VLD2007-159 ICD2007-182 pp.19-24 |
| VLD, ICD | 2008-03-07 11:10 |
Okinawa | TiRuRu | Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) VLD2007-160 ICD2007-183 |
In this paper, We Design of High Throughput Multi-rate Irregular LDPC Decoder based on Accelerated Message-Passing Sched... [more] | VLD2007-160 ICD2007-183 pp.25-30 |
| VLD, ICD | 2008-03-07 11:35 |
Okinawa | TiRuRu | Low Power Design of Accelerated Message-Passing LDPC Decoder for Long Codes Naoki Tajima, Yuta Abe, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) |
LDPC codes that quality is very close to Shannon limit become more important with the developments of radio communicatio... [more] | |
| VLD, ICD | 2008-03-07 13:00 |
Okinawa | TiRuRu | The Improvement of the Ubiqitus Processor HCgorilla Hiroki Takeda, Kazunori Noda, Atuko Yokoyama, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ) VLD2007-161 ICD2007-184 |
[more] | VLD2007-161 ICD2007-184 pp.31-36 |
| VLD, ICD | 2008-03-07 13:25 |
Okinawa | TiRuRu | An adaptive error concealment order H.264/AVC Jun Wang, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) VLD2007-162 ICD2007-185 |
[more] | VLD2007-162 ICD2007-185 pp.37-40 |
| VLD, ICD | 2008-03-07 13:50 |
Okinawa | TiRuRu | A Low-cost Speed and Yield Enhancement Method Using Embedded Delay Detectors on FPGAs Yohei Kume, Yuuri Sugihara, Ngo Cam Lai, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) VLD2007-163 ICD2007-186 |
This paper shows the principle and architecture of a low-cost speed and yield enhancement method using enbedded dela... [more] |
VLD2007-163 ICD2007-186 pp.41-46 |
| VLD, ICD | 2008-03-07 14:15 |
Okinawa | TiRuRu | Application-Oriented Dynamic Reconfigurable Network Processor Architecture and Its Optimization Method Motonori Ohta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ) VLD2007-164 ICD2007-187 |
In this paper, we propose an application directional dynamic reconfigurable network processor architecture and its optim... [more] | VLD2007-164 ICD2007-187 pp.47-52 |
| VLD, ICD | 2008-03-07 14:40 |
Okinawa | TiRuRu | Implementation and Evaluation of Network Security using An Embedded Programmable Logic Matrix (ePLX) Mitsutaka Matsumoto, Shun Kimura (Ritsumeikan Univ.), Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto (Renesas Technology Corp.), Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.) VLD2007-165 ICD2007-188 |
Low Cost Network Appliance with low power microprocessor must be connected with networks in order to realize ubiquitous ... [more] | VLD2007-165 ICD2007-188 pp.53-58 |
| VLD, ICD | 2008-03-07 15:20 |
Okinawa | TiRuRu | An Object Oriented System LSI Design Methodology and Its Evaluation Takafumi Kohara, Hiroyuki Terai, Seigo Masuoka (Kinki University), Akihisa Yamada (SHARP Corp.), Takashi Kambe (Kinki University) VLD2007-166 ICD2007-189 |
Recently there has been a number of research works reported on system level description languages and system LSI design ... [more] | VLD2007-166 ICD2007-189 pp.59-64 |
| VLD, ICD | 2008-03-07 15:45 |
Okinawa | TiRuRu | A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190 |
Reed-Solomon Decoder can correct continues error and it has been a popular technology for various devices such as commu... [more] |
VLD2007-167 ICD2007-190 pp.65-68 |
| VLD, ICD | 2008-03-07 16:10 |
Okinawa | TiRuRu | New technology of independent-gate controlled Double-Gate transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-168 ICD2007-191 |
New design technology of independent-gate controlled Double-Gate transistor realized high density design more than FinFE... [more] | VLD2007-168 ICD2007-191 pp.69-74 |
| VLD, ICD | 2008-03-07 16:35 |
Okinawa | TiRuRu | New design technology of independent-Gate controlled Stacked type 3D transistor for system LSI Yu Hiroshima, Keisuke Okamoto, Keisuke Koizumi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-169 ICD2007-192 |
New design technology of Independent-Gate controlled Stacked type 3D transistor has feature of Independent-gate controll... [more] | VLD2007-169 ICD2007-192 pp.75-80 |
| VLD, ICD | 2008-03-07 17:00 |
Okinawa | TiRuRu | Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of pattern Area Reduction with CMOS Cell Library -- Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-170 ICD2007-193 |
(To be available after the conference date) [more] | VLD2007-170 ICD2007-193 pp.81-86 |
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