Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
DC |
2014-02-10 09:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Module Coupling Overhead Aware Scan Chain Construction Meguru Komatsu, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-79 |
It is necessary to minimize the impact on the layout of the design changes to Design for Testability
(DFT). Especially,... [more] |
DC2013-79 pp.1-5 |
DC |
2014-02-10 09:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-80 |
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and
short defects since they do not behave like co... [more] |
DC2013-80 pp.7-12 |
DC |
2014-02-10 09:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] |
DC2013-81 pp.13-18 |
DC |
2014-02-10 10:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Suitable Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path Ryo Ogawa, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-82 |
The power consumption of Very Large Scale Integrated circuit (VLSI) testing is a significant problem. The VLSI should be... [more] |
DC2013-82 pp.19-24 |
DC |
2014-02-10 10:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Low Power Dissipation Oriented Don't Care Filling Method Using SAT Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ) DC2013-83 |
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captur... [more] |
DC2013-83 pp.25-30 |
DC |
2014-02-10 11:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open Yuta Nakayama (Tokyo Metro. Univ.), Masayuki Arai (Nihon Univ.), Hongbo Shi, Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2013-84 |
[more] |
DC2013-84 pp.31-36 |
DC |
2014-02-10 12:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Device-parameter Estimation Using Framework of Fmax Testing Michihiro Shintani, Takashi Sato (Kyoto Univ.) DC2013-85 |
[more] |
DC2013-85 pp.37-42 |
DC |
2014-02-10 12:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An Efficient Test Pattern Generator based on Mersenne Twister algorithm Sayaka Satonaka, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-86 |
To perform a high reliable manufacturing test with a reasonable cost, LFSR is widely used as test pattern generator. How... [more] |
DC2013-86 pp.43-48 |
DC |
2014-02-10 15:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A reduction method of shift data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ) DC2013-87 |
BAST is one of techniques to reduce the amount of test data while maintaining the high test quality using built-in self ... [more] |
DC2013-87 pp.49-54 |
DC |
2014-02-10 15:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code Ryota Mori, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-88 |
BIST-aided scan test (BAST) has been proposed as one of the techniques that enhances scan-based BIST. The BAST architect... [more] |
DC2013-88 pp.55-60 |
DC |
2014-02-10 16:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89 |
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] |
DC2013-89 pp.61-66 |
DC |
2014-02-10 16:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
An Implementation of Fault Tolerant Systems with Mutual Reconfiguration Based on Dual-FPGA Architecture Takuma Mori, Shoichi Ohmoto, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2013-90 |
This work presents a design of fault tolerant systems with mutual reconfiguration based on Dual-FPGA architecture.
The ... [more] |
DC2013-90 pp.67-72 |
DC |
2014-02-10 17:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Detection of Wormhole Attack in Wireless Sensor Network with XMesh Protocol Takashi Minohara, Aoi Yoshii (Takushoku Univ.) DC2013-91 |
In recent years, wireless sensor networks become an important technique
to monitor physical or environmental conditions... [more] |
DC2013-91 pp.73-78 |