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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-27 09:00 |
Miyagi | [Tutorial Invited Lecture]
Prospects of Intelligent Systems for Real-World Applications and Their VLSI Computing Platform Michitaka Kameyama (Tohoku Univ.)  VLD2015-33 ICD2015-46 IE2015-68 |
A computing platform for real-world intelligent systems is desired to contribute to low-cost implementation as well as h... [more] | VLD2015-33 ICD2015-46 IE2015-68 pp.37-42 |
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| RECONF | 2014-06-12 10:50 |
Miyagi | Katahira Sakura Hall | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] | RECONF2014-6 pp.27-30 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 10:35 |
Aomori | New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57 |
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] | VLD2013-57 ICD2013-81 IE2013-57 pp.59-64 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 09:25 |
Iwate | Hotel Ruiz | Design of a Packet-Transfer-Based Dynamic Reconfigurable VLSI Processor for Reduction of a Configuration Memory Size Yoshichika Fujioka (Hachinohe Inst. of Tech.), Michitaka Kameyama (Tohoku Univ.) VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | VLD2012-47 SIP2012-69 ICD2012-64 IE2012-71 pp.39-44 |
| ICD, IPSJ-ARC | 2012-01-20 15:10 |
Tokyo | An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142 |
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] | ICD2011-142 pp.93-96 |
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| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| RECONF | 2010-09-17 10:15 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33 |
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] | RECONF2010-33 pp.91-95 |
| VLD, IPSJ-SLDM | 2010-05-19 17:00 |
Fukuoka | Kitakyushu International Conference Center | Error Propagation Probability-based Selective TMR for Reliable Coarse-Grained Reconfigurable Architecture Hiroshi Yuasa, Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-4 |
Advancing CMOS process technology implies decreasing operating voltages, leaving LSI increasingly vulnerable to temporar... [more] | VLD2010-4 pp.37-42 |
| RECONF | 2009-09-18 13:35 |
Tochigi | Utsunomiya Univ. | An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36 |
This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (L... [more] | RECONF2009-36 pp.103-108 |
| SIS | 2009-06-12 10:35 |
Okinawa | VLSI Design of a Dynamic Reconfigurable MMSE Detector for 4x4 MIMO-OFDM Receiver Hirokazu Ikeuchi, Shingo Yoshizawa, Yoshikazu Miyanaga (Hokkaido Univ.) SIS2009-14 |
This report presents a VLSI architecture of dynamic reconfigurable MMSE detection in a 4x4 MIMO-OFDM receiver. MIMO-OFDM... [more] | SIS2009-14 pp.79-84 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:40 |
Fukuoka | Kitakyushu Science and Research Park | Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2008-73 DC2008-41 |
Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI... [more] | VLD2008-73 DC2008-41 pp.79-84 |
| ICD, IPSJ-ARC | 2008-05-14 11:15 |
Tokyo | Design of a Multi-Context Field-Programmable VLSI Using Ferroelectric-Based Functional Pass-Gates Noriaki Idobata, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) ICD2008-28 |
Multi-Context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching betw... [more] | ICD2008-28 pp.57-62 |
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| RCS, MoNA, WBS, SR, MW (Joint) |
2007-03-09 09:20 |
Kanagawa | YRP | Adaptive Reduction of Power Consumption of Viterbi Decoder using Reconfigurable Processor Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa (Keio Univ.) SR2006-90 |
In past time, the research that Viterbi decoder is achieved on VLSI was studied, but it was unique research that Viterbi... [more] | SR2006-90 pp.9-13 |
| RECONF | 2006-09-14 14:45 |
Kumamoto | Kumamoto Univ. | A logic design technique using SRAM blocks Masayuki Sato, Hiroki Wakamatsu (Ｇｔｉ) |
A low power on-board reconfigurable tester have been developed by using an FPGA. It is technically possible to configure... [more] | RECONF2006-23 pp.17-22 |
| ICD, IPSJ-ARC | 2006-06-09 09:30 |
Kanagawa | Voltage/Current-Control-Based Low-Power Design of a Multiple-Valued Reconfigurable VLSI Nobuaki Okada, Haque Mohammad Munirul, Michitaka Kameyama (Tohoku Univ.) |
A new reconfigurable VLSI based on multiple-valued source-coupled logic which has programmable capability is proposed fo... [more] | ICD2006-50 pp.57-61 |
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