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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SIS | 2024-06-06 16:30 |
Hiroshima | Hiroshima University (Primary: On-site, Secondary: Online) |
Hardware Implementation of Calibration Data Loading Part in Device Driver for an SPI Peripheral Hibiki Shinozaki, Akira Yamawaki (Kyutech)  SIS2024-9 |
(To be available after the conference date) [more] | SIS2024-9 pp.45-49 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| RECONF | 2018-05-24 11:20 |
Tokyo | GATE CITY OHSAKI | Prototyping of Dynamic Reconfiguration System to Execute Fallback Function Designed by High Level Synthesis Teruaki Sakata, Teppei Hirotsu (Hitachi) RECONF2018-3 |
We developed the architecture to execute a fallback operation when a failure occurred. In this research, we designed FPG... [more] | RECONF2018-3 pp.13-18 |
| RECONF | 2017-09-25 13:55 |
Tokyo | DWANGO Co., Ltd. | A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) RECONF2017-25 |
The authors consider applying FPGA Dynamic Partial Reconfiguration (DPR) technique to carrier network equipment built wi... [more] | RECONF2017-25 pp.19-24 |
| ASN | 2017-05-25 11:15 |
Tokyo | Tokyo Univ. (Institute of Industrial Science) | Development of a Sensor Network System using Dynamic Reconfigurable Devices Yusuke Yokota (Japan Women's Univ.) ASN2017-4 |
Changing behavior of working nodes is one of important functions in development of sensor nodes. Various methods for suc... [more] | ASN2017-4 pp.19-22 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-27 09:00 |
Miyagi | [Tutorial Invited Lecture]
Prospects of Intelligent Systems for Real-World Applications and Their VLSI Computing Platform Michitaka Kameyama (Tohoku Univ.) VLD2015-33 ICD2015-46 IE2015-68 |
A computing platform for real-world intelligent systems is desired to contribute to low-cost implementation as well as h... [more] | VLD2015-33 ICD2015-46 IE2015-68 pp.37-42 |
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| IN, NV (Joint) |
2015-07-16 13:00 |
Hokkaido | Hokkaido University | SDN-based Implementation of P2P Streaming Networks with Dynamic Reconfiguration Ryo Shibasaki, Noriko Matsumoto, Norihiko Yoshida (Saitama Univ.) IN2015-23 |
A P2P streaming network is tend to be unbalanced because of dynamic join and leave of its nodes, and often suffers deliv... [more] | IN2015-23 pp.1-6 |
| IN, NV (Joint) |
2015-07-16 14:50 |
Hokkaido | Hokkaido University | Dynamic Reconfiguration of P2P Streaming Networks using Network Motifs Kazuki Ono, Noriko Matsumoto, Norihiko Yoshida (Saitama Univ.) IN2015-27 |
In recent years, Peer-to-Peer (P2P) streaming networks is becoming increasing popular as it not only fault tolerant, but... [more] | IN2015-27 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:05 |
Kagoshima | [Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.) VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 |
Owing to wide spread of VLSI systems, a failure of the VLSIs may lead critical issue in our daily life. Especially in so... [more] | VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 p.183(VLD), p.81(CPM), p.81(ICD), p.27(CPSY), p.183(DC), p.69(RECONF) |
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| RECONF | 2013-09-19 14:50 |
Ishikawa | Japan Advanced Institute of Science and Technology | Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36 |
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] | RECONF2013-36 pp.97-102 |
| RECONF | 2013-05-20 17:40 |
Kochi | Kochi Prefectural Culture Hall | Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8 |
This paper proposes a mixed-grained reconfigurable architecture that supports C-based behavioral synthesis and flexibl... [more] |
RECONF2013-8 pp.41-46 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 13:25 |
Kanagawa | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84 |
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] | VLD2012-130 CPSY2012-79 RECONF2012-84 pp.135-140 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| RECONF | 2012-09-18 16:30 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-34 |
Dynamic and partial reconfiguration (DRP) on SRAM-based FPGAs has received increasing attention, since Xilinx Inc. start... [more] | RECONF2012-34 pp.61-66 |
| RECONF | 2012-09-19 09:00 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-36 |
Some of recent FPGAs have the functionality of dynamic partial reconfiguration. By using this functionality, it is expec... [more] | RECONF2012-36 pp.73-78 |
| DC, CPSY (Joint) |
2012-08-03 09:30 |
Tottori | Torigin Bunka Kaikan | A development scheduling simulater for reconfiguable system Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19 |
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] | CPSY2012-19 pp.61-66 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:30 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-73 ICD2011-76 IE2011-72 |
Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-... [more] | SIP2011-73 ICD2011-76 IE2011-72 pp.73-76 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 13:55 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) SIP2011-74 ICD2011-77 IE2011-73 |
Accelerator cores in low-power heterogeneous multicore processors have multiple memory modules to increase the data acce... [more] | SIP2011-74 ICD2011-77 IE2011-73 pp.77-82 |
| RECONF | 2011-09-26 15:30 |
Aichi | Nagoya Univ. | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow ... [more] |
RECONF2011-29 pp.43-48 |
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