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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD | 2024-01-29 10:55 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Suppression of output bit width growth in AFE stochastic computing units Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.)  VLD2023-81 RECONF2023-84 |
Stochastic Computing (SC) is expected to be applied to fields such as image processing and machine learning. Amplitude a... [more] | VLD2023-81 RECONF2023-84 pp.7-12 |
| CPSY, DC, IPSJ-ARC [detail] | 2021-07-21 14:00 |
Online | Online | CPSY2021-8 DC2021-8 |
(To be available after the conference date) [more] | CPSY2021-8 DC2021-8 pp.43-48 |
| NS, ICM, CQ, NV (Joint) |
2020-11-27 14:00 |
Online | Online | Distributed vRouter Acceleration using FPGA on IA Server Kazuki Hyoudou, Takashi Shimizu, Ryo Miyashita (Fujitsu Labs.), Hiroshi Murakawa (Fujitsu KCN), Tomohiro Ishihara (Fujitsu Labs.) NS2020-84 |
Recently, the virtualization of network functions, or NFV, becomes common. And libraries to implement high performance d... [more] | NS2020-84 pp.49-55 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2020-02-27 15:10 |
Kagoshima | Yoron-cho Chuou-Kouminkan | Accelerating Change-Point Detection on Multiple Multidimensional Stream Data using FPGA NIC Takuma Iwata, Hiroki Matsutani (Keio Univ.) CPSY2019-94 DC2019-100 |
(To be available after the conference date) [more] | CPSY2019-94 DC2019-100 pp.13-18 |
| RECONF | 2019-09-19 16:00 |
Fukuoka | KITAKYUSHU Convention Center | The Implementation of Binarized YOLO System on Low-cost FPGA Kaijie Wei, Koki Honda, Hideharu Amano (Keio) RECONF2019-32 |
State-of-the-art AI application on low-end edge device faces two challenges: high energy utilization and resources defic... [more] | RECONF2019-32 pp.63-68 |
| CPSY, DC, IPSJ-ARC [detail] | 2018-06-15 12:50 |
Yamagata | Takamiya Rurikura Resort | FPGA and DPDK-Based Communication Acceleration Methods for Prediction Server with Multiple Predictors Kaho Okuyama, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani (Keio Univ.) CPSY2018-5 DC2018-5 |
(To be available after the conference date) [more] | CPSY2018-5 DC2018-5 pp.101-106 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 10:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Automatic Conversion from Snort PCRE to Verilog HDL Masahiro Fukuda, Yasushi Inoguchi (JAIST) VLD2017-78 CPSY2017-122 RECONF2017-66 |
In this paper, we present how to automatically convert Snort's PCRE (Perl Compatible Regular Expressions) into Verilog H... [more] | VLD2017-78 CPSY2017-122 RECONF2017-66 pp.95-100 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-23 12:10 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan | FPGA and DPDK-Based Communication Acceleration Methods for Parameter Servers Kazumasa Kishiki, Korechika Tamura, Hiroki Matsutani (Keio Univ.) RECONF2017-19 |
(To be available after the conference date) [more] | RECONF2017-19 pp.99-104 |
| ET | 2017-03-10 12:45 |
Ehime | National Institute of Technology, Niihama College | Design of a training program for logic circuit and arithmetic algorithm learning using programmable devices Shigeki Abe (Tohoku Univ.) ET2016-112 |
(To be available after the conference date) [more] | ET2016-112 pp.105-110 |
| NC, NLP (Joint) |
2017-01-26 11:20 |
Fukuoka | Kitakyushu Foundation for the Advanement of Ind. Sci. and Tech. | On LabVIEW FPGA Implementation of Chaotic Neuron Toshihiro Tachibana, Hideaki Okazaki (Shonan Institute of Tech.) NLP2016-101 |
In recent years, FPGA (field-programmable gate array) such as dynamically reconfigurable devices has attracted attention... [more] | NLP2016-101 pp.25-30 |
| RECONF | 2014-06-12 09:25 |
Miyagi | Katahira Sakura Hall | Optimized HOG for database system Mao Hatto, Takaaki Miyajima, Hiroki Matsutani, Hideharu Amano (Keio Univ.) RECONF2014-3 |
As technology of High Performance Computing and Pattern Recognition has evolved rapidly, Human Detection system also ha... [more] |
RECONF2014-3 pp.11-16 |
| CPSY, DC | 2014-04-25 15:15 |
Tokyo | A Hardware Cache Mechanism for Column-Oriented Databases Akihiko Hamada, Hiroki Matsutani (Keio Univ.) CPSY2014-5 DC2014-5 |
A column-oriented store is one of structured storages (NOSQLs), in which a variable number of columns can be stored for... [more] |
CPSY2014-5 DC2014-5 pp.21-26 |
|
| EA | 2010-12-10 11:05 |
Ibaraki | Univ. of Tsukuba | Hardware speech recognition system for processing and recognition at moment Masashi Nakayama (KNCT), Naoki Shigekawa (Univ. of Fukui), Takashi Yokouchi (KNCT) EA2010-99 |
In this paper, we are proposed the hardware speech recognition system using FPGA (Field-Programmable Gate Array). Genera... [more] | EA2010-99 pp.13-18 |
| ICD | 2010-04-22 15:20 |
Kanagawa | Shonan Institute of Tech. | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 |
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] | ICD2010-9 pp.47-52 |
| DC, CPSY | 2010-04-13 17:20 |
Tokyo | Fault-tolerant FPGA Architecture Takashi Okada, Takanobu Kita, Ryota Shioya, Masahiro Goshima, Shuichi Sakai (Tokyo Univ.) CPSY2010-7 DC2010-7 |
Since electric devices for space applications are likely to experience radiation induced errors, such as the Single Even... [more] | CPSY2010-7 DC2010-7 pp.33-37 |
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| VLD, ICD, DC, IPSJ-SLDM | 2005-12-01 09:30 |
Fukuoka | Kitakyushu International Conference Center | Delay Testing for Application-Specific Interconnects of FPGAs based on Inphase Structure Kosuke Yabuki, Satoshi Ohtake, Hideo Fujiwara (NAIST) |
This paper presents a method of path delay fault testing for application-specific interconnects in field-programmable ga... [more] | VLD2005-61 ICD2005-156 DC2005-38 pp.1-6 |
| RECONF | 2005-09-16 09:00 |
Hiroshima | Programmable Numerical Function Generators: Architectures and Synthesis Method Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I.T), Jon T. Butler (Naval Postgraduate School) |
This paper presents an architecture and a synthesis method for programmable numerical function generators (NFGs) of trig... [more] | RECONF2005-41 pp.1-6 |
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