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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 13:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC)  VLD2022-92 HWS2022-63 |
In this paper, we propose CNFET7, the first open-source cell library for7-nm carbon nanotube field-effect transistor (CN... [more] | VLD2022-92 HWS2022-63 p.110 |
| RECONF | 2020-05-29 10:50 |
Online | Online | Proposal of Reconfigurable Device Placement Algorithm Using Placement Quality Judgment Neural Network as Cost Function of SA Method Yuichi Natsume, Tokio Kamada, Kubota Atsushi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2020-13 |
The circuit performance of reconfigurable devices greatly depends on the place-and-route results, so optimal place-and-r... [more] | RECONF2020-13 pp.71-76 |
| NS, IN (Joint) |
2020-03-06 11:00 |
Okinawa | Royal Hotel Okinawa Zanpa-Misaki (Cancelled but technical report was issued) |
Laplace Equation-Based High-Speed Autonomous Clustering for MANET Rio Kawasaki (Tokyo Metropolitan Univ.), Chisa Takano (Hiroshima City Univ.), Masaki Aida (Tokyo Metropolitan Univ.) IN2019-117 |
In MANET, autonomous decentralized clustering technologies of terminals for hierarchical route control have been studied... [more] | IN2019-117 pp.231-236 |
| RECONF | 2019-09-19 14:00 |
Fukuoka | KITAKYUSHU Convention Center | A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech) RECONF2019-21 |
The placement of an FPGA design is performed using the simulated annealing algorithm with a cost function predicting wir... [more] | RECONF2019-21 pp.3-8 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:25 |
Hiroshima | Satellite Campus Hiroshima | Quality determination of logic element placement using deep learning in fine grain reconfigurable device MPLD Hidehito Fujiishi, Tokio Kamada, Tetsuo Hironaka, Kazuya Tanigawa, Atsushi Kubota (Hiroshima city Univ.) VLD2018-48 DC2018-34 |
In CAD for MPLD which is a type of fine grain reconfigurable PLD, the SA method is used as a place-ment method for logic... [more] | VLD2018-48 DC2018-34 pp.71-76 |
| ICD, CPSY, CAS | 2017-12-14 15:10 |
Okinawa | Art Hotel Ishigakijima | An Almost Digitally Synthesizable SAR-ADC Kenshu Komatsu, Zule Xu, Takayuki Kawahara (TUS) CAS2017-95 ICD2017-83 CPSY2017-92 |
We are considering the stakelization of ADC, which is indispensable in integrated circuits, especially trying to realize... [more] | CAS2017-95 ICD2017-83 CPSY2017-92 p.135 |
| SIP, CAS, MSS, VLD | 2017-06-19 10:40 |
Niigata | Niigata University, Ikarashi Campus | Placement Algorithm for Mixed-Grained Reconfigurable Architecture with Dedicated Carry Chain Koki Honda, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4 |
This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) f... [more] | CAS2017-4 VLD2017-7 SIP2017-28 MSS2017-4 pp.19-24 |
| NS | 2016-01-22 15:30 |
Fukuoka | Content-Oriented Traffic Engineering with Content Caching Yusaku Hayamizu, Kouji Hirata, Miki Yamamoto (Kansai Univ.) NS2015-165 |
Recently, many content-oriented schemes have been proposed for network design which is suitable for services required by... [more] | NS2015-165 pp.109-114 |
|
| CS | 2014-11-07 09:00 |
Hokkaido | Shiretoko (Hokkaido) | Time to Hold (TTH), an Optimal Cache Replacement Policy for Video Delivery on CCN Haipeng Li, Hidenori Nakazato (Waseda Univ.) CS2014-65 |
In-network caching, one of the characteristics of Content Centric Networking (CCN), allows the contents to be cached alo... [more] | CS2014-65 pp.69-74 |
| IN, IA (Joint) |
2013-12-20 09:20 |
Hiroshima | Hiroshima City Univ. | Cache Replacement Method using Round-Trip Time in Content-Centric Networking Kenji Yokota, Kohei Sugiyama, Atsushi Tagami (KDDI R&D Labs) IN2013-110 |
In this paper, we propose a cache replacement method using rout-trip time (RTT) in content-centric networking (CCN). CCN... [more] | IN2013-110 pp.65-70 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:35 |
Kagoshima | Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55 |
In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture for reconf... [more] |
RECONF2013-55 pp.87-92 |
|
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 09:10 |
Kanagawa | Architecture Evaluation of a Reconfigurable Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) VLD2012-107 CPSY2012-56 RECONF2012-61 |
In this paper, we discuss the detailed structure of MPLD, an architecture for realizing reconfigurable devices. MPLD co... [more] |
VLD2012-107 CPSY2012-56 RECONF2012-61 pp.1-6 |
|
| IN, MoNA (Joint) |
2012-11-21 17:40 |
Fukuoka | Fukuoka Institute of Technology | [Invited Talk]
Research Trends of Wireless Mesh Networks and the Future Makoto Ikeda (FIT) IN2012-115 MoMuC2012-36 |
In recent years, mobile communication traffic has been increasing rapidly. A flexible network with high system capacity ... [more] | IN2012-115 MoMuC2012-36 pp.27-32(IN), pp.21-26(MoMuC) |
| IN, MoNA (Joint) |
2012-11-22 13:15 |
Fukuoka | Fukuoka Institute of Technology | A Study on Different Genetic Operators for Mesh Router Placement Using Multi-Objective Genetic Algorithms Tetsuya Oda, Shinji Sakamoto, Makoto Ikeda, Leonard Barolli (FIT) MoMuC2012-37 |
Communication is performed through a mesh router in a wireless mesh network users. Therefore, the placement of the mesh ... [more] | MoMuC2012-37 pp.27-31 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 15:25 |
Kanagawa | Hiyoshi Campus, Keio University | Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) |
(To be available after the conference date) [more] | |
| PRMU, HIP | 2010-03-16 12:20 |
Kagoshima | Kagoshima Univ. | Research on three dimension route presumption with acceleration sensor Ryota Anraku, Masayuki Kashima, Kiminori Sato, Mutsumi Watanabe (Kagoshima Univ.) PRMU2009-295 HIP2009-180 |
Nowadays GPS (Global Positioning System) is used as estimation of present place and movement route estimation of migrati... [more] | PRMU2009-295 HIP2009-180 pp.365-370 |
| RECONF | 2009-09-17 14:50 |
Tochigi | Utsunomiya Univ. | Low-power oriented clustering and placement tools using routability for FPGAs Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2009-23 |
Power consumption of Field Programmable Gate Arrays (FPGAs) is larger than Application Specific Integrated Circuits (ASI... [more] | RECONF2009-23 pp.25-30 |
| VLD | 2009-03-12 13:50 |
Okinawa | A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147 |
An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip. It is difficult to incre... [more] |
VLD2008-147 pp.123-128 |
|
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-21 14:40 |
Fukuoka | Kitakyushu International Conference Center | An approach to Place and Route challenges in Dynamic Reconfiguration Ryo Hidaka, Fuminori Kobayashi (Kyushu Inst. of Tech.), Minoru Watanabe (Shizuoka Univ.) RECONF2007-38 |
Recently, though the dynamically reconfigurable devices begin to be practical, these devices change the circuit with tim... [more] | RECONF2007-38 pp.13-17 |
| CPSY | 2007-10-26 09:00 |
Kumamoto | Kumamoto University | An examination of hardware acceleration in FPGA placement based on SA Yoshio Sonokawa, Yuji Ariuchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2007-30 |
Placement is one of the steps that expend the time in the FPGA (Field Programmable Gate Array) design automation flow. ... [more] |
CPSY2007-30 pp.33-38 |
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