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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS)  VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| HWS, VLD | 2019-02-27 13:05 |
Okinawa | Okinawa Ken Seinen Kaikan | Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-97 HWS2018-60 |
In this report, we consider a wire load model for an FPGA using new nano-device called via-switch to allow power estimat... [more] | VLD2018-97 HWS2018-60 pp.25-30 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 09:00 |
Hiroshima | Satellite Campus Hiroshima | Resources Utilization of Fine-grained Overlay Architecture Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37 |
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] | RECONF2018-37 pp.15-20 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 11:05 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2017-80 CPSY2017-124 RECONF2017-68 |
This paper quantitatively shows the superiority of 0-1-$A$-$overline{A}$ LUT to 0-1 LUT in terms of area, delay time and... [more] | VLD2017-80 CPSY2017-124 RECONF2017-68 pp.107-112 |
| SIP, CAS, MSS, VLD | 2017-06-19 11:40 |
Niigata | Niigata University, Ikarashi Campus | An Implementation Method of Reconfigurable Network Intrusion Detection Systems Based on Random Forests Binbin Xue, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.) CAS2017-7 VLD2017-10 SIP2017-31 MSS2017-7 |
In this paper, we propose an implementation method of reconfigurable network intrusion detection system based on random ... [more] | CAS2017-7 VLD2017-10 SIP2017-31 MSS2017-7 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| RECONF | 2014-06-12 10:50 |
Miyagi | Katahira Sakura Hall | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] | RECONF2014-6 pp.27-30 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 10:35 |
Aomori | New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57 |
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] | VLD2013-57 ICD2013-81 IE2013-57 pp.59-64 |
|
| RECONF | 2013-09-18 17:00 |
Ishikawa | Japan Advanced Institute of Science and Technology | A Restricted Dynamically Reconfigurable Architecture for Low Power Processors Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-24 |
Reconfigurable processors have widely attracted attention as an approach to realize high-performance and highly energy-e... [more] | RECONF2013-24 pp.25-30 |
| DC | 2013-06-21 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core Kentaroh Katoh (TNCT) DC2013-14 |
This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The pr... [more] | DC2013-14 pp.25-29 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:00 |
Iwate | Hotel Ruiz | Accelerator Architecture for Multi Scale Filter Operation Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 |
Image recognition processing includes a number of filter operations which dominate the total execution time. Exploiting... [more] |
VLD2012-51 SIP2012-73 ICD2012-68 IE2012-75 pp.59-64 |
| DC, CPSY (Joint) |
2012-08-02 16:15 |
Tottori | Torigin Bunka Kaikan | Co-processor of a low power accelerator CMA Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2012-14 |
Cool Mega-Array (CMA) is a novel high performance but low power reconfigurable accelerator consisting of a large PE(Proc... [more] | CPSY2012-14 pp.31-36 |
| SR | 2012-05-24 17:15 |
Kanagawa | Keio univ. at Hiyoshi | [Panel Discussion]
Multi-band operation for mobile terminals Shoichi Narahashi, Hiroshi Okazaki, Atsushi Fukuda, Takayuki Furuta, Kunihiro Kawai, Kei Satoh, Yuta Takagi (NTT DOCOMO) SR2012-12 |
It is a key issue for radio frequency (RF) circuits of future mobile terminals to equip with multi-band operation archit... [more] | SR2012-12 pp.73-78 |
| ICD, IPSJ-ARC | 2012-01-20 15:10 |
Tokyo | An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142 |
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] | ICD2011-142 pp.93-96 |
|
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:20 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] | SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| US | 2011-09-26 15:15 |
Miyagi | Tohoku Univ. | System flexibility of medical ultrasound equipment Takaya Uno (Hitachi Aloka Medical,Ltd.) US2011-49 |
Commercial Medical Ultrasound Equipment is combined hardware and software very complexly. Thus, many researchers cannot ... [more] | US2011-49 pp.17-21 |
| SCE | 2011-07-13 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High-Throuput Bit-Slice Multipliers Using SFQ Circuits Yohei Naruse, Nobutaka Kito, Naofumi Takagi (Kyoto Univ.) SCE2011-9 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have... [more] | SCE2011-9 pp.47-52 |
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