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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2012-04-24 14:50 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas)  ICD2012-15 |
The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, nanoscale fully-depleted MOSFETs (FD MOS) a... [more] | ICD2012-15 pp.79-84 |
| SDM, ICD | 2011-08-26 13:40 |
Toyama | Toyama kenminkaikan | Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) SDM2011-89 ICD2011-57 |
An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] | SDM2011-89 ICD2011-57 pp.93-97 |
| SDM, ICD | 2011-08-26 14:05 |
Toyama | Toyama kenminkaikan | Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Riichiro Takemura, Tomonori Sekiguchi, Kiyoo Itoh (Hitachi) SDM2011-90 ICD2011-58 |
[more] | SDM2011-90 ICD2011-58 pp.99-102 |
| ICD | 2011-04-18 10:00 |
Hyogo | Kobe University Takigawa Memorial Hall | [Invited Talk]
Trends and Multi-level-cell Technology of Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) ICD2011-1 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magnetic tunnel junctions) was devel... [more] | ICD2011-1 pp.1-5 |
| SDM | 2010-11-11 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Trends of Magnetic Memory; Multi-Level-Cell Spin Transfer Torque Memory Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) SDM2010-173 |
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magneto tunnel junctions) was develo... [more] | SDM2010-173 pp.11-15 |
| ICD | 2010-04-22 15:45 |
Kanagawa | Shonan Institute of Tech. | A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] | ICD2010-10 pp.53-57 |
| ITE-MMS, MRIS | 2009-10-08 13:55 |
Fukuoka | FUKUOKA traffic center | [Invited Talk]
Nonvolatile RAM using spin transfer torque magnetization reversal (SPRAM) Hiromasa Takahashi, Kenchi Ito, Jun Hayakawa, Katsuya Miura, Hiroyuki Yamamoto, Michihiko Yamanouchi (ARL, Hitachi, Ltd.), Kazuo Ono, Riichiro Takemura, Takayuki Kawahara (CRL, Hitachi, Ltd.), Ryutaro Sasaki (RIEC Tohoku Univ.), Haruhiro Hasegawa (RIEC Tohoku Univ., ARL, Hitachi, Ltd.), Shoji Ikeda (RIEC Tohoku Univ.), Hideyuki Matsuoka (ARL, Hitachi, Ltd.), Hideo Ohno (RIEC Tohoku Univ.) |
The SPRAM (Spin Transfer Torque MRAM) is one of nonvolatile memories that “writing” is done by that a magnetization in M... [more] | |
| ICD | 2009-04-13 13:30 |
Miyagi | Daikanso (Matsushima, Miyagi) | [Invited Talk]
Trend in Multi-Gigabit DRAM Technology and Low-Vt Small-Offset Gated Preamplifier for Sub-1-V Arrays Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh (Hitachi, Ltd.,) ICD2009-2 |
[more] | ICD2009-2 pp.7-12 |
| ICD, SDM | 2007-08-24 15:15 |
Hokkaido | Kitami Institute of Technology | SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for suppressing read disturbance and write-current dispersion Katsuya Miura, Takayuki Kawahara, Riichiro Takemura (Hitachi, Ltd.), Jun Hayakawa (Hitachi, Ltd./Tohoku Univ.), Michihiko Yamanouchi (Hitachi, Ltd.), Shoji Ikeda, Ryutaro Sasaki (Tohoku Univ.), Kenchi Ito, Hiromasa Takahashi, Hideyuki Matsuoka (Hitachi, Ltd.), Hideo Ohno (Tohoku Univ.) SDM2007-166 ICD2007-94 |
SPin-transfer torque RAM (SPRAM) with MgO-barrier-based magnetic tunnel junctions (MTJs) is a promising candidate for a ... [more] | SDM2007-166 ICD2007-94 pp.135-138 |
| ICD | 2007-04-12 13:00 |
Oita | [Invited Talk]
2-Mb SPRAM (SPin-transfer torque RAM) with Bit-by-bit Bi-Directional Current Write and Parallelizing-Direction Current Read Riichiro Takemura, Takayuki Kawahara, Katsuya Miura (Hitachi), Jun Hayakawa (Hitachi/Tohoku Univ.), Shoji Ikeda, Young Min LEE, Ryutaro Sasaki (Tohoku Univ.), Yasushi Goto, Kenchi Ito (Hitachi), Toshiyasu Meguro, Fumihiro Matsukura (Tohoku Univ.), Hiromasa Takahashi (Hitachi/Tohoku Univ.), Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2007-6 |
A 1.8-V 2-Mb SPRAM (SPin-transfer torque RAM) chip using 0.2 µm logic process with MgO tunneling barrier cell demo... [more] | ICD2007-6 pp.29-34 |
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| ICD, ITE-CE | 2006-01-26 10:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Phase Change RAM Operated with 1.5-V CMOS as Low Cost Embedded Memory Satoru Hanzawa, Kenichi Osada, Takayuki Kawahara, Riichiro Takemura (Hitachi CRL), Naoki Kitai (Hitachi ULSI), Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi (Hitachi CRL), Hiroshi Moriya (Hitachi MERL), Masahiro Moniwa (Renesas) |
This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, u... [more] | ICD2005-206 pp.7-12 |
| ICD, SDM | 2005-08-19 13:50 |
Hokkaido | HAKODATE KOKUSAI HOTEL | A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa (Hitachi), Kazuhiko Kajigaya (ELPIDA), Takayuki Kawahara (Hitachi) |
We propose and evaluate a DRAM cell array with 12-F2 twin cell in terms of speed, retention time, and low-voltage operat... [more] | SDM2005-152 ICD2005-91 pp.55-60 |
| ICD | 2005-04-14 14:30 |
Fukuoka | [Invited Talk]
Statistical Integration In Multigigabit DRAM Design Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] | ICD2005-8 pp.37-42 |
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