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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| MW (2nd) |
2017-06-14 - 2017-06-16 |
Overseas | KMUTT, Bangkok, Thailand | [Short Paper]
RF Characteristics of SOTB Devices for GHz Frequency Applications Van-Trung Nguyen, Koichiro Ishibashi (UEC) |
The paper presents RF characteristics of the 65nm SOTB CMOS devices for 1GHz range. With many superior features such as ... [more] | |
| ICD, CPSY | 2016-12-15 15:30 |
Tokyo | Tokyo Institute of Technology | [Poster Presentation]
Integer DCT for H.265/HEVC using 65 nm SOTB process Kazuyoshi Noda, Cong-Kha Pham (Univ of Electro-Communications)  ICD2016-90 CPSY2016-96 |
In recent years, an increase in the amount of data has become a problem due to the increase in resolution of video equip... [more] | ICD2016-90 CPSY2016-96 p.117 |
| AP (2nd) |
2016-02-29 17:00 |
Overseas | Telecommunications University, Nha Trang, Vietnam | An ASIC Implementation of Hardware Logarithm Generator for Digital Signal Processing in Communication Systems Van-Thuan Sai, Van-Phuc Hoang (LQDTU) |
In this paper, we present an efficient hardware approximation for the binary logarithm function which is highly required... [more] | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:35 |
Oita | B-ConPlaza | Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-84 DC2014-38 |
Recently, the growth of power consumption has been serious by process scaling. The lower voltage is most effective to i... [more] |
VLD2014-84 DC2014-38 pp.93-97 |
| SR | 2013-10-24 13:00 |
Osaka | Osaka Univ. | [Technology Exhibit]
Radio Receiver Front-End Using Time-Based ADC Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichirou Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada (DENSO), Hou Yu, Yoshiyuki Hirooka, Ninh Hong Phuc, Masaya Miyahara, Akira Matsuzawa (Tokyo Inst. of Tech.) SR2013-62 |
A direct-conversion RF-receiver implemented in 65nm CMOS which has RF front-end and Time-Based analog-to-digital convert... [more] | SR2013-62 pp.49-54 |
| RECONF | 2011-09-26 10:45 |
Aichi | Nagoya Univ. | Wavepipelining on A Ultra Low Power Reconfigurable Accelerator CMA-1. Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (The Univ. of Electro-Communications) RECONF2011-22 |
CMA(Cool Mega-Array)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 PEs wi... [more] | RECONF2011-22 pp.1-6 |
| RECONF | 2011-05-13 10:45 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Optimization of Application Programs of SLD-1 : A Low Power Accelarator Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Tech. Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Tokyo Univ. of Electro-Communication) RECONF2011-15 |
SLD(Silent Large Datapath)-1 is a prototype media accelerator consisting of a large PE array which includes 24bit 8 × 8 ... [more] | RECONF2011-15 pp.85-90 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 15:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Real Chip evaluation of Silent Large Datapath:A Ultra Low Power Accelarater Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-110 CPSY2010-65 RECONF2010-79 |
Battery driven multi-media applications require both high performance and energy efficiency. Recon-figurable... [more] | VLD2010-110 CPSY2010-65 RECONF2010-79 pp.175-180 |
| SDM, VLD | 2007-10-30 15:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.) VLD2007-59 SDM2007-203 |
We have developed a system consisting of a full-3D process simulator for stress calculation and k·pband calculation... [more] | VLD2007-59 SDM2007-203 pp.43-46 |
| ICD | 2007-04-13 09:40 |
Oita | [Invited Talk]
A 65 nm Embedded SRAM with Wafer Level Burn-In Mode, Leak-Bit Redundancy and E-trim Fuse for Known Good Die Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono (Renesas Technology), Yuji Oda (Shikino High-Tech), Susumu Imaoka (Renesas Design), Keiichi Usui (Daioh Electric), Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) ICD2007-11 |
We propose a Wafer Level Burn-In (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair s... [more] | ICD2007-11 pp.59-64 |
|
| ICD, SDM | 2006-08-18 12:05 |
Hokkaido | Hokkaido University | A 65 nm Ultra-High-Density Dual-port SRAM with 0.71um2 8T-cell for SoC Susumu Imaoka (Renesas Design), Koji Nii (Renesas Technology), Yasuhiro Masuda (Renesas Design), Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Motoshige Igarashi, Kazuo Tomita, Nobuo Tsuboi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) |
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stabi... [more] | SDM2006-148 ICD2006-102 pp.133-136 |
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