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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT)  VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| CPSY, DC (Joint) |
2014-07-29 09:00 |
Niigata | Toki Messe, Niigata | Verification Method of the Split Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism Kazuya Matsuda (TAT), Takefumi Miyoshi (e-trees.Japan), Masashi Takemoto (TAT), Satoshi Funada (e-trees.Japan), Hironori Nakajo (TAT) CPSY2014-17 |
In recent years, a high-level synthesis tool has been attracted in designing hardware circuits instead of traditional HD... [more] | CPSY2014-17 pp.43-48 |
| CPSY, DC (Joint) |
2014-07-29 10:45 |
Niigata | Toki Messe, Niigata | Interconnect Design for Low Latency, High Topological Embeddability and Partitioning Capability by Supplementary Optical Circuit Switches Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII) CPSY2014-20 |
This paper focuses on how to efficiently run multiple small parallel applications in a single High-performance computing... [more] | CPSY2014-20 pp.61-66 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:25 |
Kanagawa | Hiyoshi Campus, Keio University | A Storing and Regenerating Signal Information in a Scalable Hardware System Yusuke Katoh, Daisuke Watanabe, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech) VLD2013-106 CPSY2013-77 RECONF2013-60 |
In implementing a large-scale circuit into a single LSI, limitation of circuit area or degradation of maximum operating ... [more] | VLD2013-106 CPSY2013-77 RECONF2013-60 pp.25-30 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | Hardware Expansion Protocol in a Scalable Hardware System Daisuke Watanabe, Yusuke Katoh, Hironori Nakajo (Tokyo Univ. of Agriculture and Tech.) VLD2013-107 CPSY2013-78 RECONF2013-61 |
Recently hardware acceleration with using an FPGA are focused as well as prototyping an ASIC with it. The available numb... [more] | VLD2013-107 CPSY2013-78 RECONF2013-61 pp.31-36 |
| RECONF | 2013-05-21 10:10 |
Kochi | Kochi Prefectural Culture Hall | Design and Evaluation of FPGA-based ASIC Emulator using High-speed Serial Communication Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2013-10 |
Recently, development period of ASIC is longer becouse of the increase in circuit scale. Verification process accounts ... [more] |
RECONF2013-10 pp.49-54 |
| CAS, NLP | 2011-10-20 14:20 |
Shizuoka | Shizuoka Univ. | Fast Simulation of Multiconductor System with Nonlinear Devices by Using Block-Latency Insertion Method and Reduced Order Model Tadatoshi Sekine, Hideki Asai (Shizuoka Univ.) CAS2011-41 NLP2011-68 |
This paper describes a fast circuit simulation technique based on the block-latency insertion method (block-LIM) and a m... [more] | CAS2011-41 NLP2011-68 pp.49-54 |
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 14:10 |
Kanagawa | Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.) VLD2008-119 CPSY2008-81 RECONF2008-83 |
For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circ... [more] | VLD2008-119 CPSY2008-81 RECONF2008-83 pp.165-170 |
|
| SIP, CAS, CS | 2007-03-06 09:30 |
Tottori | Blancart Misasa (Tottori) | [Poster Presentation]
Computation reduction in linear transform circuit synthesis using genetic algorithm Mai Suzuki, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) CAS2006-97 SIP2006-198 CS2006-114 |
A linear transform circuit is often used in various transform such as DCT and DFT. In realizing in hardware, it is impor... [more] | CAS2006-97 SIP2006-198 CS2006-114 pp.23-27 |
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