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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ICD 2022-10-25
15:40
Shiga
(Primary: On-site, Secondary: Online)
Hardware Acceleration of TFHE-based Adder by Controlling Error
Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] HWS2022-40 ICD2022-32
pp.58-63
HWS, VLD 2019-03-01
10:00
Okinawa Okinawa Ken Seinen Kaikan Synthesis of Full Hardware Implementation of RTOS-Based Systems
Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85
This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time... [more]
VLD2018-122 HWS2018-85
pp.175-180
EE 2018-01-30
09:00
Oita Satellite Campus Oita Adaptive Controlled High Power Efficiency Dual Active Bridge DC-DC Converter
Soejima Takaaki, Yoichi Ishizuka (Nagasaki Univ.), Toshiro Hirose (Nishimu Electronics Industries Co.) EE2017-64
Hard switching and switching surge are critical issues in Dual Active Bridge (DAB) DC-DC converter under the light load.... [more] EE2017-64
pp.127-132
EE, IEE-HCA 2017-05-26
15:10
Tokyo The Kikai Shinko Kaikan building Realization of ZVS and Current Surge Suppression Technique for DAB DC-DC Converter with Proposed Masked Switching and PFM Control
Takaaki Soejima, Yoichi Ishizuka (Nagasaki Univ.), Toshiro Hirose (Nishimu Electronics Industries) EE2017-7
Hard switching and switching surge are critical issues in Dual Active Bridge (DAB) DC-DC converter under the light load.... [more] EE2017-7
pp.69-74
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-30
11:45
Osaka Ritsumeikan University, Osaka Ibaraki Campus A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD) VLD2016-67 DC2016-61
Due to outsourcing of numerous stages of the IC manufacturing process in different foundries, security risks such as har... [more] VLD2016-67 DC2016-61
pp.135-140
NLP, CCS 2015-06-11
10:55
Tokyo Waseda Univerisity Amplitude Switching Phenomena in Coupled Networks of Hard Type Oscillators
Ryota Hirano, Takuya Kitamura, Seiichiro Moro (Univ. Fukui) NLP2015-43 CCS2015-5
In this study, we investigate the oscillation phenomena in a random-coupled network of hard-type oscillators whose nonli... [more] NLP2015-43 CCS2015-5
pp.25-30
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-26
17:30
Oita B-ConPlaza A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry.
This circumstan... [more]
VLD2014-91 DC2014-45
pp.135-140
NLP 2011-03-10
15:20
Tokyo Tokyo University of Science Propagating pulse wave observed in a ring of six-coupled hard-type van der Pol oscillators -- A case starting from type 2 standing wave --
Kyohei Kamiyama (Meiji University), Motomasa Komuro (Teikyo Univ. of Sci.), Tetsuro Endo (Meiji University), Kuniyasu Shimizu (Chiba Inst. of Tech.) NLP2010-175
We investigate bifurcation of Type 2-periodic solution in a ring of 6 coupled hard-type van der Pol oscillators. As a re... [more] NLP2010-175
pp.69-76
SCE 2005-07-27
11:35
Aomori Hirosaki Univ. Automatic logic synthesis scheme and tool implementation for Single-Flux-Quantum circuits
Yoshio Kameda, Shinichi Yorozu, Yoshihito Hashimoto (SRL)
Single-flux-quantum (SFQ) logic circuits provide us a faster operation with low power consumption using Josephson juncti... [more] SCE2005-17
pp.27-32
 Results 1 - 9 of 9  /   
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