Print edition: ISSN 0913-5685
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VLD2006-119
A Processing Unit Optimization Algorithm in SIMD Processor Cores Design
Hiroyuki Shigeta, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 1 - 6
VLD2006-120
A Hardware/Software Partitioning Framework for SIMD Processor Cores
Masataka Ohigashi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 7 - 12
VLD2006-121
SIMD Instructions Generation Algorithm for Multiple Loop for SIMD Processor Cores Optimum Design
Hiroki Nakajima, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 13 - 18
VLD2006-122
An Application Specific Data Optimization System for Processor Cores and Its Experimental Evaluation
Kazuhisa Horiuchi, Shunitsu Kohara, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 19 - 24
VLD2006-123
An efficient design methodology for image processing digital system by using a high level hardware description language
Satoru Inoue, Taiki Hashizume, Tomonori Izumi, Masahiro Fukui (Ritsumeikan Univ.)
pp. 25 - 30
VLD2006-124
Mixed Analog-Digital Fully-Parallel Associative Memory with Search
Yuki Tanaka, Md. Anwarul Abedin, Tetsushi Koide, Mattausch. Hans Juergen (Hiroshima Univ.)
pp. 31 - 36
VLD2006-125
A 90-nm SRAM for Video Signal Processors implementing Dynamic Voltage and Frequency Scaling
Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
pp. 37 - 42
VLD2006-126
A Clock Deskew Method Using Statisical Presumption
Naoki Ootani, Yuko Hashizume, Yasuhiro Takashima (Univ. of Kitayushu), Yuichi Nakamura (NEC)
pp. 43 - 48
VLD2006-127
A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits
Yousuke Harada, Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech.)
pp. 49 - 53
VLD2006-128
Low Power and High Speed Clock Distribution Technique for 90-nm CMOS LSIs
Yousuke Hagiwara, Suguru Nagayama, Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
pp. 55 - 60
VLD2006-129
The Potential Router
Yoji Kajitani (Univ. of Kitakyushu)
pp. 61 - 66
VLD2006-130
Escape Fitting between a Pair of Pin-Sets
Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu)
pp. 67 - 72
VLD2006-131
BGA Routing by The Potential Router
Takayuki Hiromatsu, Masato Inagi, Yasuhiro Takashima, Yoji Kajitani (Univ. of Kitakyushu)
pp. 73 - 78
VLD2006-132
Automatic routing methods which make modification after routing easy
Toshihiko Yokomaru, Takahide Yoshikawa, Yuzi Kanazawa (Fujitsu Labs.)
pp. 79 - 84
VLD2006-133
Relocation Method for Circuit Modification
Kunihiko Yanagibashi, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC)
pp. 85 - 90
VLD2006-134
A CAM Emulator Using Look-Up Table Cascades
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
pp. 91 - 96
VLD2006-135
Design Method of Radix Converters Using Arithmetic Decompositions (3)
Yukihiro Iguchi (Meiji Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT), Toshikazu Aoyama (Meiji Univ.)
pp. 97 - 102
VLD2006-136
Design of RSA Encryption circuit with embedded Fixed Private Key using Via Programmable Logic VPEX
Hiroshi Shimomura, Kazuki Okuyama, Akihiro Nakamura, Takeshi Fujino (Ritsumei Univ.)
pp. 103 - 108
VLD2006-137
Programmable CMOS Analog Circuit with Body Biasing
Youhei Ide, Toru Fujimura, Shinya Takeshita, Masatoshi Nakamura, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 109 - 114
VLD2006-138
Novel fast digital background calibration for pipelined ADC's
Takashi Oshima (Hitachi), Cheonguyrn Tsang, Cheonguyrn Tsang (UC Berkeley)
pp. 115 - 120
VLD2006-139
[Invited Talk]
Measurements and reduction of power line noises in SoCs
Makoto Ikeda, Kunihiro Asada (Tokyo Univ.)
pp. 121 - 126
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.