Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2010-116
An Architecture Exploration Method based on a Branch-and-Bound Strategy for Embedded VLIW Processors
Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)
pp. 1 - 6
VLD2010-117
Energy-Aware Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors with Multi-Cycle Instructions
Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)
pp. 7 - 12
VLD2010-118
Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.)
pp. 13 - 18
VLD2010-119
Intra-task Analysis of Worst Case Execution Time and Average Energy Consumption on DEPS Framework
Hirotaka Kawashima, Gang Zeng, Noritoshi Atsumi, Tomohiro Tatematsu, Hiroaki Takada (Nagoya Univ.)
pp. 19 - 24
VLD2010-120
An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization
Yoshinori Shimada, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 25 - 30
VLD2010-121
Investigation and Evaluation of Sleep Signal Control based on a History Information for Fine-grain Power Gating
Tetsuya Muto, Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 31 - 36
VLD2010-122
Low Power Design of Digital Circuits using Quasi-complementary MOS Gates
Shuichi Sowa, Mineo Kaneko (JAIST)
pp. 37 - 42
VLD2010-123
Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration
Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 43 - 47
VLD2010-124
[Fellow Memorial Lecture]
Understanding CMOS Variability for More Moore
Hidetoshi Onodera (Kyoto Univ./JST)
p. 49
VLD2010-125
Semi-static TSPC DFF Using Split-output Latch
Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo (Mie Univ.)
pp. 51 - 56
VLD2010-126
Implementation and Security Evaluation of DPA-Resistant DES Circuit utilizing Domino-RSL technique
Katsuhiko Iwai, Kenji Kojima, Mitsuru Shiozaki, Syunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.)
pp. 57 - 62
VLD2010-127
Evaluation of Delay-Time Difference Distribution for the Delay-Time Difference Measurable Arbiter-PUF
Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Akitaka Fukushima, Takeshi Fujino (Ritsumeikan Univ.)
pp. 63 - 68
VLD2010-128
A Low Power Hardware Architecture for Parallel Group Signature Computation
Sumio Morioka, Jun Furukawa, Kazue Sako (NEC)
pp. 69 - 74
VLD2010-129
A scalable hardware architecture for real time image recognition
Takashi Aoki, Eiichi Hosoya, Takuya Otsuka, Akira Onozawa (NTT)
pp. 75 - 80
VLD2010-130
A Circuit Synthesis for High Speed Memory Access in System LSI
Kazuya Kishida, Takashi Kambe (Kinki Univ.)
pp. 81 - 86
VLD2010-131
A Circuit Synthesis for Dynamic Reconfigurable Processor
Nobuyuki Araki, Takashi Kambe (Kinki Univ.)
pp. 87 - 92
VLD2010-132
A Circuit Design and Its Evaluation for Correlation Caluculation in Particle Tracking System
Shouta Moriguchi, Takashi Kambe (Kinki Univ.)
pp. 93 - 98
VLD2010-133
Delay Variation-Aware Datapath Synthesis for Improved Performance and Tunability
Dang Yu, Mineo Kaneko (JAIST)
pp. 99 - 104
VLD2010-134
A Study for Evaluation of Statistical Maximum Operations for Gaussian Mixture Models
Tamotsu Ishihara, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
pp. 105 - 110
VLD2010-135
Performance Evaluation of Statistical Static Timing Analysis Using Gaussian Mixture Models
Tomoyuki Fujimori, Shuji Tsukiyama (Chuo Univ), Masahiro Fukui (Ritsumeikan Univ)
pp. 111 - 116
VLD2010-136
Delay Analysis of Sub-Path on Fabricated Chips by Several Path-delay Tests
Takanobu Shiki, Yasuhiro Takashima (Univ.of Kitakyushu), Yuichi Nakamura (NEC Corp.)
pp. 117 - 122
VLD2010-137
A Routing Method for Multi-Layer Single Flux Quantum Circuits with Wire Ordering based on Slack Allocation
Shota Takeshima, Kazuyoshi Takagi, Masamitsu Tanaka (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)
pp. 123 - 128
VLD2010-138
CRP : Efficient Topology Modification for Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (Univ. of Kitakyushu), Atsushi Takahashi (Osaka Univ.)
pp. 129 - 134
VLD2010-139
Fast Algorithm for All-Pair Shortest Path on DAG using CUDA
Akihide Yamamura, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 135 - 139
VLD2010-140
On Realization and Evaluation of Capacitors in Analog Integrated Circuits
Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu)
pp. 141 - 146
VLD2010-141
An evaluation of error detection/correction circuits by gate level simulation
Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.)
pp. 147 - 152
VLD2010-142
Behavior Verification of a Variable Latency Circuit on FPGA
Yuuta Ukon (Osaka Univ), Masafumi Inoue (Tokyo Tech), Atsushi Takahashi, Kenji Taniguchi (Osaka Univ)
pp. 153 - 158
VLD2010-143
Acceleration of Bounded Model Checking for Sequential Circuits with Two-phase Verification
Norihiro Ono, Kazuhiro Nakamura, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)
pp. 159 - 164
VLD2010-144
Write Optimization for High-speed Non-volatile Memory Using Next State Function
Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.)
pp. 165 - 170
VLD2010-145
A scalable prototyping system for 3D-stacked LSI development
Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST)
pp. 171 - 175
VLD2010-146
Performance Evaluation of Via Programmable ASIC Architecture VPEX3
Taisuke Ueoka, Tatsuya Kitamori, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 177 - 182
VLD2010-147
Evaluation of Wiring Resource and Wiring Delay used in Via Programmable Logic Device VPEX
Tatsuya Kitamori, Ryohei Hori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 183 - 188
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.