Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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ICD2011-100
An Inductorless Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS
Sang-Yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech.)
pp. 1 - 6
ICD2011-101
[Invited Talk]
Challenging of semiconductor capability for comfortable human life
-- Future engineers, what's the role and skill --
Kazutami Arimoto (Renesas Electronics)
pp. 7 - 11
ICD2011-102
[Invited Talk]
Tamper LSI Design Methodology using Physical Unclonable Function
Takeshi Fujino, Kota Furuhashi, Mitsuru Shiozaki (Ritsumeikan Univ.)
pp. 13 - 18
ICD2011-103
A study of the simulation methodology to analyze DC-DC converter's characteristics in high-speed and precice without using SPICE circuit simulator
Tatsuya Furukawa, Yuya Hirano, Yasuhiro Sugimoto (Chuo Univ.)
pp. 19 - 24
ICD2011-104
[Poster Presentation]
The design of TDC and ADPLL circuits considering metastable operations
Yasuyuki Shimizu (Osaka Inst. Tech.), Giichi Sakemi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.)
pp. 25 - 27
ICD2011-105
[Poster Presentation]
Broadband Low Noise Amplifier Design in Scaled CMOS Technology
Ben Patrick (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.)
pp. 29 - 34
ICD2011-106
[Poster Presentation]
Analog Circuit Design in Scaled CMOS Technologies
Ying Yang, Jingbo Shi, Ben Patrick, Takayuki Konishi (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.)
pp. 35 - 40
ICD2011-107
[Poster Presentation]
A Implementation Technique of a Multibit Successive Approximation Register AD Converter
Naoya Kunikata, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.)
pp. 41 - 45
ICD2011-108
[Poster Presentation]
Low-Power High-Speed Rail-to-Rail Voltage Buffer for LCD Drivers
Yousuke Tsukamoto, Cong-Kha Pham (UEC)
pp. 47 - 52
ICD2011-109
[Poster Presentation]
Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits
Yasushi Kishiwada, Shun Ueda, Yusuke Miyawaki, Toshimasa Matsuoka (Osaka Univ.)
pp. 53 - 55
ICD2011-110
[Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits.
Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.)
pp. 57 - 58
ICD2011-111
[Poster Presentation]
Comparator for A/D converter using time-to-digital converter
Naoki Isobe, Toshimasa Matsuoka, Kenji Taniguchi (Osaka Univ.)
pp. 59 - 61
ICD2011-112
[Poster Presentation]
Analysis of the Neural Spike Recording Amplifier with Telescopic OPA
Chisato Takatsuki, Takeshi Yoshida (Hiroshima Univ.)
pp. 63 - 65
ICD2011-113
[Poster Presentation]
Efficient Execution of Floating Point Instructions in CRIB
Naoaki Ohkubo, Kenji Kise (TokyoTech)
p. 67
ICD2011-114
[Poster Presentation]
Sleep Depth Controlling for Run-Time Leakage Power Saving
Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura (Tokyo Univ.)
p. 69
ICD2011-115
[Poster Presentation]
A study of a 1.5V operational cyclic current-mode ADC utilizing the pipeline conversion architecture
Masatoshi Kamuro, Masanobu Ota, Yasuhiro Sugimoto (Chuo Univ.)
pp. 71 - 74
ICD2011-116
[Poster Presentation]
Endurance enhancement programming method for 50nm resistive random access memory (ReRAM)
Kazuhide Higuchi, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi (Univ. of Tokyo)
pp. 75 - 80
ICD2011-117
[Poster Presentation]
4-Times Faster Rising Vpass (10V), 15% Lower Power Vpgm (20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives
Teruyoshi Hatanaka, Ken Takeuchi (Tokyo Univ.)
pp. 81 - 86
ICD2011-118
[Poster Presentation]
An oscillator-based true random number generator with jitter amplifier
Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
pp. 87 - 92
ICD2011-119
[Poster Presentation]
Estimation of Soft Error Rate on a Via Programmable Logic "VPEX"
Taisuke Ueoka, Ryohei Hori, Tatsuya Kitamori (Ritsumeikan Univ), Masaya Yoshikawa (MeijoUniv), Takeshi Fujino (Ritsumeikan Univ)
pp. 93 - 98
ICD2011-120
[Poster Presentation]
Via programmable analog circuit (VPA): New approach for analog circuits
Ryo Nakazawa, Ryohei Hori, Keisuke Ueda, Mitsuru Shiozaki, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ)
pp. 99 - 103
ICD2011-121
[Poster Presentation]
Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling
Igors Homjakovs, Masanori Hashimoto (Osaka Univ.), Tetsuya Hirose (Kobe Univ.), Takao Onoye (Osaka Univ.)
pp. 105 - 107
ICD2011-122
[Poster Presentation]
A Study on High Resolution SAR ADC
Toyoki Asazawa, Yoshihiro Tsunokawa, Masaya Miyahara, Akira Matsuzawa (Titech)
p. 109
ICD2011-123
[Poster Presentation]
High Linearity Open-loop Amplifier for Interpolated Pipeline ADC
Yoshiyuki Hirooka, Hyunui Lee, Masaya Miyahara, Akira Matsuzawa (Titech)
p. 111
ICD2011-124
[Poster Presentation]
A 60GHz CMOS Direct-conversion Transceiver
Tatsuya Yamaguchi, Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Ryo Minami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa (Titech)
p. 113
ICD2011-125
[Poster Presentation]
Designing Technique of a Single-Differential LNA
Takahiro Masumoto, Daisuke Kanemoto, Haruichi Kanaya (Kyushu Univ.), Ramesh Pokharel (E-JUST center), Keiji Yoshida (Kyushu Univ.)
pp. 115 - 117
ICD2011-126
[Invited Talk]
To be a worldwide researcher!
-- Challenges to DAC and ISSCC --
Shingo Takahashi (NEC)
pp. 119 - 122
ICD2011-127
[Tutorial Lecture]
Technology Trends in ISSCC TD(Technology Direction)
Masaitsu Nakajima (Panasonic Corp.)
p. 123
ICD2011-128
[Invited Talk]
Ultra-Low Voltage and Extremely-Low Power Logic Circuit Design
Hiroshi Fuketa (Univ. Tokyo)
pp. 125 - 130
ICD2011-129
A 65-nm Radiation-Hard Flip-Flop Tolerant to Multiple Cell Upsets
Ryosuke Yamamoto, Chikara Hamanaka (Kyoto Inst. of Tech.), Jun Furuta (Kyoto Univ.), Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 131 - 136
ICD2011-130
Hardware software co-design methodology tolerating software redundancy
Yuta Teranishi (Fujitsu Qnet), Toshiya Otomo, Koji Kurihara, Hiromasa Yamauchi, Takahisa Suzuki, Koichiro Yamashita (Fujitsu Lab)
pp. 137 - 142
ICD2011-131
[Invited Talk]
Power Noise in VLSI Chip
-- from Silicon Substrate to Electromagnetic Environment --
Makoto Nagata (Kobe Univ.)
pp. 143 - 148
ICD2011-132
A 284-uW 1.85-GHz 20-Phase Oscillator Using Transfer Gate Phase Couplers
Keisuke Okuno, Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 149 - 154
ICD2011-133
0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation
Shusuke Yoshimoto, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.)
pp. 155 - 160
ICD2011-134
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure
Yohei Umeki, Shusuke Yoshimoto, Takurou Amashita, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST)
pp. 161 - 166
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.