Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2011-120
Global Process Parameter Estimation Using IDDQ Current Signature
Michihiro Shintani, Takashi Sato (Kyoto Univ.)
pp. 1 - 6
VLD2011-121
Performance evaluation and Improvement of Via Programmable Logic VPEX
Taku Otani, Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 7 - 12
VLD2011-122
LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip
Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST)
pp. 13 - 17
VLD2011-123
An Evaluation of the Speedup Method for Power Grid Circuit Simulation by GPGPU
Hayato Shiono, Lei Lin, Makoto Yokota, Masahiro Fukui (Ritsumeikan Univ.)
pp. 19 - 24
VLD2011-124
10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control
Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT)
pp. 25 - 30
VLD2011-125
Implementation of Tamper-Resistant Cryptographic DES Circuit using Dual-Rail RSL Memory
Megumi Shibatani, Katsuhiko Iwai, Mitsuru Shiozaki, Shunsuke Asagawa, Takeshi Fujino (Ritsumeikan Univ.)
pp. 31 - 36
VLD2011-126
A loop pipeling method for irregular nested loops
Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS)
pp. 37 - 42
VLD2011-127
Resource Binding for Datapaths with Improved Post-Silicon Skew Tunability
Yosuke Haruta, Mineo Kaneko (JAIST)
pp. 43 - 48
VLD2011-128
High-Level Synthesis for Mixed Behavioral-Level/RTL Design Descriptions
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
pp. 49 - 54
VLD2011-129
CDFG Transformation Based on Speculation Exploiting Implicit Parallelism in Behavioral Synthesis
Shinji Ohno (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
pp. 55 - 60
VLD2011-130
Utilization of Register Transfer Level False Paths for Logic Optimization with Logic Synthesis Tools
Takehiro Mikami, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 61 - 66
VLD2011-131
A Length Matching Routing Algorithm on Single Layer Using Longer Path Algorithm for Single Net
Syouhei Furuyama, Yukihide Kohira (UoA)
pp. 67 - 72
VLD2011-132
A Power Grid Optimization Algorithm Considering by NBTI
Yoriaki Nagata, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
pp. 73 - 78
VLD2011-133
Design automation of highly reliable VLSI by redundancy FF replacement method
Ken Yano, Takahito Yoshiki, Takanori Hayashida, Toshinori Sato (Fukuokadai)
pp. 79 - 84
VLD2011-134
An Efficient Method to Analyze Logic Masking Effects of Soft Errors in Sequential Circuits
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.)
pp. 85 - 90
VLD2011-135
Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits
Takahiro Kawaguchi (Nagoya Univ.), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.)
pp. 91 - 96
VLD2011-136
Implmentation of Look-ahead Assertion for Pattern-independent Regular Expression Matching Engine
Yoichi Wakaba, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 97 - 102
VLD2011-137
An Implementation of Real-time Image Recognition Hardware for Many Cameras
Eiichi Hosoya, Takashi Aoki, Takuya Otsuka, Yusuke Sekihara, Akira Onozawa (NTT)
pp. 103 - 108
VLD2011-138
Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor
Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 109 - 114
VLD2011-139
A GPGPU Implementation of Approximate Regular Expression Matching Algorithm and Comparison with an FPGA Implementation
Yuichiro Utan, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 115 - 120
VLD2011-140
Power Efficient Design of Arithmetic Circuits Based on Embedded Memory Blocks in FPGA
Xinmu Yu (Waseda Univ.), Kiyoharu Hamaguchi (Osaka Univ.), Shinji Kimura (Waseda Univ.)
pp. 121 - 126
VLD2011-141
Performance of the Evaluation of a Variable-Latency-Circuit on FPGA
Yuuta Ukon, Kenta Ando, Atsushi Takahashi (Osaka Univ)
pp. 127 - 132
VLD2011-142
Power-Switch Drive-circuit generation for Ground-Bounce reduction using the Genetic-Programming
Makoto Miyauchi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 133 - 138
VLD2011-143
A Design of Low-Power Color Interporation Circuits Based on Color Difference
Kouta Omobayashi, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 139 - 144
VLD2011-144
Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch
Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 145 - 150
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.