IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 117, Number 444

Dependable Computing

Workshop Date : 2018-02-20 / Issue Date : 2018-02-13

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Table of contents

DC2017-77
Note on Weighted Fault Coverage for Two-Pattern Tests
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.)
pp. 1 - 6

DC2017-78
A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation
Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
pp. 7 - 12

DC2017-79
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 13 - 18

DC2017-80
Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech)
pp. 19 - 24

DC2017-81
A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.)
pp. 25 - 30

DC2017-82
On generating locating arrays using simulated annealing
Tatsuya Konishi, Hideharu Kojima, Hiroyuki Nakagawa, Tatsuhiro Tsuchiya (Osaka Univ.)
pp. 31 - 35

DC2017-83
A Note on Stateless Avoidance Routing in Ad Hoc Networks
Tomonori Maeda, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
pp. 37 - 42

DC2017-84
A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue (NAIST), Alex Orailoglu (Univ. of California, San Diego)
pp. 43 - 48

DC2017-85
A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor
Kenji Inoue, Yousuke Miyake, Seiji Kajihara (Kyutech)
pp. 49 - 54

DC2017-86
Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 55 - 60

DC2017-87
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD)
Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN)
pp. 61 - 66

DC2017-88
Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures
Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.)
pp. 67 - 72

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan