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Special Interest Group on System Architecture (IPSJ-ARC) (Searched in: 2021)
Search Results: Keywords 'from:2022-01-24 to:2022-01-24'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 09:30 |
Online | Online | Study on a Correlation Controlling Method to Realize Correlation-used Calculations Sequentially in Stochastic Computing Shu Zhang, Shigeru Yamashita (Ritsumeikan Univ.)  VLD2021-49 CPSY2021-18 RECONF2021-57 |
Stochastic Computing (SC) is an approximation calculation method using Stochastic Number (SN), which represents the exis... [more] | VLD2021-49 CPSY2021-18 RECONF2021-57 pp.1-6 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 09:55 |
Online | Online | Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.) VLD2021-50 CPSY2021-19 RECONF2021-58 |
In this study, we propose reverse converters for moduli set ${2^k,2^n+1,2^n-1}$ that convert residue number system to we... [more] | VLD2021-50 CPSY2021-19 RECONF2021-58 pp.7-12 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 11:25 |
Online | Online | FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation Kaoru Yamamoto, Takayuki Kawahara (TUS) VLD2021-53 CPSY2021-22 RECONF2021-61 |
Annealing machines can be classified into sparsely coupled types and fully coupled types. The fully coupled type has the... [more] | VLD2021-53 CPSY2021-22 RECONF2021-61 pp.25-30 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 11:50 |
Online | Online | Multi-spin-flip method for Ising machines and its application Tatsuhiko Shirai, Nozomu Tagawa (Waseda Univ.) VLD2021-54 CPSY2021-23 RECONF2021-62 |
(To be available after the conference date) [more] | VLD2021-54 CPSY2021-23 RECONF2021-62 pp.31-36 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 13:15 |
Online | Online | [Invited Talk]
A Challenge of Research, Development, Manufacturing, and Marketing of Quantum Computing Control Systems Takefumi Miyoshi (QuEL, Inc./e-trees.Japan, Inc./Osaka Univ.) VLD2021-55 CPSY2021-24 RECONF2021-63 |
[more] | VLD2021-55 CPSY2021-24 RECONF2021-63 p.37 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:25 |
Online | Online | () VLD2021-56 CPSY2021-25 RECONF2021-64 |
The current development of simulators and machine learning technologies in science and technology is expected to lead to... [more] | VLD2021-56 CPSY2021-25 RECONF2021-64 pp.38-42 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 15:55 |
Online | Online | Accelerating Deep Neural Networks on Edge Devices by Knowledge Distillation and Layer Pruning Yuki Ichikawa, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Titech) VLD2021-58 CPSY2021-27 RECONF2021-66 |
A deep neural network (DNN) is computationally expensive, making it challenging to run DNN on edge devices. Therefore, m... [more] | VLD2021-58 CPSY2021-27 RECONF2021-66 pp.49-54 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 16:20 |
Online | Online | Addition of DPU Training Function by Tail Layer Training Yuki Takashima, Akira Jinguji, Hiroki Nakahara (Tokyo Tech) VLD2021-59 CPSY2021-28 RECONF2021-67 |
The demand for deep learning has been increasing, and many hardware implementations have been proposed. The Deep learnin... [more] | VLD2021-59 CPSY2021-28 RECONF2021-67 pp.55-60 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 16:45 |
Online | Online | A study of an accelerator for CNN inference on FPGA clusters Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS) VLD2021-60 CPSY2021-29 RECONF2021-68 |
In this study, we propose a CNN accelerator for FPGA clusters, which accelerates the CNN inference process by distributi... [more] | VLD2021-60 CPSY2021-29 RECONF2021-68 pp.61-66 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 17:10 |
Online | Online | Ternarizing Deep Spiking Neural Network Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima (NAIST) VLD2021-61 CPSY2021-30 RECONF2021-69 |
The feasibility of ternarizing spiking neural networks (SNNs) is studied in this work toward trading a slight accuracy f... [more] | VLD2021-61 CPSY2021-30 RECONF2021-69 pp.67-72 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 09:30 |
Online | Online | GPU acceleration of algorithm for minimal distance approximate calculation between two objects Masumi Fukuta, Takakazu Kurokawa, Takashi Matsubara, Keisuke Iwai (NDA) VLD2021-62 CPSY2021-31 RECONF2021-70 |
(To be available after the conference date) [more] | VLD2021-62 CPSY2021-31 RECONF2021-70 pp.73-77 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 09:55 |
Online | Online | An Accuracy-Aware Data Size Reduction Method of 3D Lidar SLAM Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) VLD2021-63 CPSY2021-32 RECONF2021-71 |
(To be available after the conference date) [more] | VLD2021-63 CPSY2021-32 RECONF2021-71 pp.78-83 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 10:20 |
Online | Online | FPGA Implementation of Radar Imaging for Walk-Through Security Screening System Tatsuya Sumiya, Yuki Kobayashi, Masayuki Ariyoshi (NEC) VLD2021-64 CPSY2021-33 RECONF2021-72 |
To enhance security at facilities such as railway stations and commercial buildings where many people come and go withou... [more] | VLD2021-64 CPSY2021-33 RECONF2021-72 pp.84-89 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 10:45 |
Online | Online | An Implementation of a Real-time Stereo Matching System on FPGA Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.) VLD2021-65 CPSY2021-34 RECONF2021-73 |
To make full use of stereo data in autonomous driving system, the techniques to generate depth-map in real-time are nece... [more] | VLD2021-65 CPSY2021-34 RECONF2021-73 pp.90-95 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 11:25 |
Online | Online | A Light-Weight Machine Learning based Packet Routing using Online Sequential Learning Kenji Nemoto, Masaki Furukawa, Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.) VLD2021-66 CPSY2021-35 RECONF2021-74 |
[more] | VLD2021-66 CPSY2021-35 RECONF2021-74 pp.96-101 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 11:50 |
Online | Online | VLD2021-67 CPSY2021-36 RECONF2021-75 |
(To be available after the conference date) [more] | VLD2021-67 CPSY2021-36 RECONF2021-75 pp.102-107 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 13:15 |
Online | Online | A Study on Technology mapping method for Scalable Logic Module Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.) VLD2021-68 CPSY2021-37 RECONF2021-76 |
The LUT (Lookup Table) , which is widely used as the logic cell in FPGA (Field Programmable Gate Array）, can implement a... [more] | VLD2021-68 CPSY2021-37 RECONF2021-76 pp.108-113 |
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