Tue, Nov 12 PM Welcome & Opening Remarks
12:45 - 13:00 |
| |
12:45-13:00 |
Welcome & Opening Remarks ( 15 min. ) |
Tue, Nov 12 PM
13:00 - 13:50 |
(1)
VLD |
13:00-13:50 |
[Keynote Address]
Development of MN-Core AI Oriented Processor in Preferred Networks |
Jun Makino (PFN/Kobe U.) |
Tue, Nov 12 PM
14:05 - 15:20 |
(2)
VLD |
14:05-14:30 |
Low-bit Quantization Methods for Neural Networks |
Emi Wada, Shinji Kimuda (Waseda Univ.) |
(3)
VLD |
14:30-14:55 |
Efficient inference method using adaptive variable time steps in SNN |
Naoya Watanabe, Yoshinori Takeuchi (Kindai) |
(4)
VLD |
14:55-15:20 |
New Cluster Architecture and Clustering Method Using PAE Cells for eFPGA IP |
Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ) |
Tue, Nov 12 PM
14:05 - 15:20 |
(5)
ICD |
14:05-14:30 |
Power Reduction Technique for Low Noise Amplifier in Random Undersampling Compressed Sensing EEG Measurement System |
Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.) |
(6)
ICD |
14:30-14:55 |
Low Power ΔΣ Modulator With Low Voltage OTA for Wearable Application |
Naoya Maruyama, Satoshi Komatsu (Tokyo Denki Univ.) |
(7)
ICD |
14:55-15:20 |
Design of a Low-Energy MTJ-Based Nonvolatile Register Storing Differential Information |
Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu (Tohoku Uviv.) |
| |
15:20-15:35 |
Break ( 15 min. ) |
Tue, Nov 12 PM
15:35 - 17:15 |
(8)
RECONF |
15:35-16:00 |
FPGA Implementation of Multiplication-Free Table-Lookup-Based CNN Accelerator |
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki (AIST) |
(9)
RECONF |
16:00-16:25 |
Evaluation of Techniques for Ultra-Long Bit-Width Floating-Point Arithmetic on FPGAs |
Shintaro Kawasaki, Kuwazawa Gen, Yoshiki Yamaguchi (Univ. Tsukuba) |
(10)
RECONF |
16:25-16:50 |
Implementation and Evaluation of Arithmetic Masking to Mitigate Side-channel Attacks on Wavefront Array-based DNN Accelerator |
Hirokatsu Yamasaki, Kota Yoshida, Yuta Fukuda, Takeshi Fujino (Ritsumeikan Univ) |
(11)
RECONF |
16:50-17:15 |
Accelerating CRS Format Conversion for Sparse Matrix Computation with FPGA |
Tomoya Yokono, Yoshiki Ymaguchi (Univ of Tsukuba) |
Tue, Nov 12 PM
15:35 - 17:15 |
(12)
DC |
15:35-16:00 |
On Reducing Area Overhead of Pseudo-Random Pattern Generator in BIST for Approximate Multiplier |
Daichi Akamatsu, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ) |
(13)
DC |
16:00-16:25 |
On design of a delay testable circuit with an embedded arbiter PUF |
Hayato Miki, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ) |
(14)
DC |
16:25-16:50 |
Design of SNU-tolerant non-volatile Flip-Flop |
Kyotaro Takahashi, Kazuteru Namba (Chiba Univ.) |
(15)
DC |
16:50-17:15 |
Evaluating Soft Error Tolerance and Proposing an Error Detection Method for TFHE Applications Running on GPUs (*) |
Masakazu Yoshida, Kotaro Matsuoka, Masanori Hashimoto (Kyoto Univ.) |
Tue, Nov 12 PM
17:15 - 18:45 |
| (16) |
17:15-18:45 |
|
Wed, Nov 13 AM
09:00 - 10:15 |
(17)
VLD |
09:00-09:25 |
Utilization of Signal Similarity in Compressed Sensing
-- Realizing Low-power Dissipation Wireless EEG Monitoring Circuit System -- |
Daisuke Kanemoto, Eichi Takimoto, Tetsuya Hirose (Osaka Univ.) |
(18)
VLD |
09:25-09:50 |
Application of Simulated Annealing to Wireless EEG Measurement in Compressed Sensing |
Shodai Motomochi, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ) |
(19)
VLD |
09:50-10:15 |
Development of a Random Undersampling SARADC in a Wireless EEG Measurement System Utilizing Compressed Sensing |
Takuma Matsumoto, Daisuke Kanemoto, Wataru Okumura, Riku Matsubara, Tetsuya Hirose (Osaka Univ) |
Wed, Nov 13 AM
09:00 - 10:15 |
(20)
ICD |
09:00-09:25 |
Low Dropout Regurator Sizing using Bayesian Optimization |
Tsuyoshi Masubuchi (GU), Nobukazu Takai (KIT) |
(21)
ICD |
09:25-09:50 |
Comparison of Analog Circuit Sizing Performance in Bayesian Optimization using Algorithms for Higher Dimensions |
Ryo Takagi (KIT), Tsuyoshi Masubuchi (Gunma Univ.), Yuto Moriguchi, Nobukazu Takai (KIT) |
(22)
ICD |
09:50-10:15 |
Enhancing the Efficiency of Analog Integrated Circuits using by Explainable AI |
Takayoshi Namura, Yuto Moriguchi, Nobukazu Takai (KIT) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Wed, Nov 13 AM
10:30 - 11:45 |
(23)
VLD |
10:30-10:55 |
Study on a Scalable Chopper-Stabilized Auto-Zero Amplifier for Wireless EEG Measurement |
Yukito Yoshikawa, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ) |
(24)
VLD |
10:55-11:20 |
Validation of a design methodology for security systems using compressed sensing and chain-generated noise masking. |
Tomoya Yamamoto, Daisuke Kanemoto, Ryota Tsunaga, Tetsuya Hirose (Osaka Univ) |
(25)
VLD |
11:20-11:45 |
Temperature sensor with Time-to-Digital Converter for low-voltage operation |
Kaito Nagai, Kimiyoshi Usami (SIT) |
Wed, Nov 13 AM
10:30 - 11:20 |
(26)
ICD |
10:30-10:55 |
Prametric Yield Estimation using Bayesian Neural Networks |
Yuto Moriguchi, Nobukazu Takai (KIT) |
(27)
ICD |
10:55-11:20 |
Digital Circuit Topology Search Using Genetic Algorithm with Block Structure |
Hikaru Horikawa, Nobukazu Takai (KIT) |
| |
11:45-13:00 |
Break ( 75 min. ) |
Wed, Nov 13 PM
13:00 - 13:50 |
(28)
ICD |
13:00-13:50 |
[Keynote Address]
Development of Ultra-Low Power Material-Based AI Edge System |
Hirofumi Tanaka (Kyutech) |
| |
13:50-14:05 |
Break ( 15 min. ) |
Wed, Nov 13 PM
14:05 - 14:55 |
(29)
RECONF |
14:05-14:55 |
[Keynote Address]
Supporting Academic Innovation using Arm Technologies |
Tsung-Chih Su, Takayuki Yokoyama (ARM) |
| |
14:55-15:10 |
Break ( 15 min. ) |
Wed, Nov 13 PM
15:10 - 16:25 |
(30)
RECONF |
15:10-15:35 |
Implementarion of Multi-Channel Fast Audio Convolution on FPGA |
Masatsugu Okazaki (Yamaha), Ryuji Kawashima, Ryosuke Takagi (YHD) |
(31)
RECONF |
15:35-16:00 |
A Preliminary Evaluation of fDTM-PUF with TDC Sensor for Controlled Threshold |
Kazuki Fujimoto, Yuta Fukuda, Tatsuya Oyama (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.) |
(32)
RECONF |
16:00-16:25 |
A Low-Cost Point Cloud Deep Learning Model Using Neural ODE for FPGAs |
Mizuki Yasuda, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
Wed, Nov 13 PM
15:10 - 16:25 |
(33)
VLD |
15:10-15:35 |
|
|
(34)
VLD |
15:35-16:00 |
|
Ryusei Eda, Nozomu Togawa (Waseda Univ.) |
(35)
VLD |
16:00-16:25 |
Cryogenic Transistor Current Modeling Based on Sparse Gaussian Process Regression |
Tetsuro Iwasaki (KIT), Takashi Sato (KU), Michihiro Shintani (KIT) |
| |
16:25-16:40 |
Break ( 15 min. ) |
Wed, Nov 13 PM
16:40 - 17:55 |
(36)
ICD |
16:40-17:05 |
Development of generative AI-based automated design technology for AI chips |
Yasutaka Serizawa, Hisanori Matsumoto (Hitachi) |
(37)
ICD |
17:05-17:30 |
A development of Adaptive Bias Attachment for Low-Power Analog Circuit Design |
Shunsuke Akahoshi, Nobukazu Takai (KIT) |
(38)
ICD |
17:30-17:55 |
Effects of Input Signal Power on Nonlinear Amplifiers in Semantic Communication |
Qijian Zhang, Daisuke Umehara, Nobukazu Takai (KIT) |
Wed, Nov 13 PM
16:40 - 17:55 |
| (39) |
16:40-17:05 |
|
| (40) |
17:05-17:30 |
|
| (41) |
17:30-17:55 |
|
Wed, Nov 13 PM
18:30 - 20:30 |
| (42) |
18:30-20:30 |
|
Thu, Nov 14 AM
08:45 - 09:00 |
| |
08:45-09:00 |
( 15 min. ) |
Thu, Nov 14 AM
09:00 - 10:15 |
(43)
RECONF |
09:00-09:25 |
Implementation and Performance Evaluation of an FPGA-Based Electronic Circuit Simulator with a Speculative Execution Linear Solver using Gauss-Jordan Elimination and the BiCGSTAB Method |
Yuya Shuto, Yuma Omoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) |
(44)
RECONF |
09:25-09:50 |
Proposal for NV of Logic Cell Architecture for eFPGA IP |
Keizo Hiraga (SSS), Kensu Seto, Masahiro Iida (Kumamoto Univ), Kazuhiro Bessho (SSS) |
(45)
RECONF |
09:50-10:15 |
"Enhancing VPN Gateway Performance through Reconfigurable Hardware Acceleration |
Kenji Tanaka, Naoki Miura, Takeshi Sakamoto (NTT) |
Thu, Nov 14 AM
09:00 - 10:15 |
| (46) |
09:00-09:25 |
|
| (47) |
09:25-09:50 |
|
| (48) |
09:50-10:15 |
|
| |
10:15-10:30 |
Break ( 15 min. ) |
Thu, Nov 14 AM
10:30 - 11:45 |
(49)
VLD |
10:30-10:55 |
LSI Design and Tape-Out Case Studies Using Open-Source EDA |
Masakazu Hioki, Toshihiro Katashita, Yohei Hori, Hiroshi Fuketa, Ippei Akita (AIST) |
(50)
VLD |
10:55-11:20 |
A Study on the Validity of Logic Synthesis Result Selection with Imposed Design Constraints |
Masashi Imai (Hirosaki Univ.) |
(51)
VLD |
11:20-11:45 |
Student lab. for entry of the semiconductor education with Agile-chip platform |
Hideharu Amano, Atsushi Kosuge, Naonobu Shimamoto, Toru Mogami, Yukinori Ochiai, Hirofumi Sumi, Makoto Ikeda, Yoshio Mita (U. Tokyo) |
Thu, Nov 14 AM
10:30 - 11:45 |
(52)
ICD |
10:30-10:55 |
An Evaluation of Lightweight Hash for Message Authentication Code in CMOS Image Sensors |
Manami Hagizaki, Hiroaki Ogawa, Oyama Tatsuya, Takeshi Fujino, Okura Shunsuke (Ritsumeikan Univ.) |
(53)
ICD |
10:55-11:20 |
On-chip contact angle sensor using coplanar capacitors |
Hayato Fukui, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture) |
(54)
ICD |
11:20-11:45 |
Impact of Size Effect on Delay Time of On-Chip Interconnects under Cryogenic Conditions |
Tatsuya Ueda, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ Shiga Prefecture) |
| |
11:45-13:00 |
Break ( 75 min. ) |
Thu, Nov 14 PM
13:00 - 13:20 |
| (55) |
13:00-13:20 |
|
Thu, Nov 14 PM
13:20 - 14:10 |
(56)
ICD |
13:20-14:10 |
[Invited Talk]
Annual Report of A Start-Up Community for Open-Source Silicon in Japan. |
Noritsuna Imamura (ISHI-Kai), Akira Tsuchiya (The University of Shiga Prefecture), Takeshi Kuboki (Kumamoto Univ.), Mizuki Mori (Keio Univ.) |
| |
14:10-14:25 |
Break ( 15 min. ) |
Thu, Nov 14 PM
14:25 - 15:15 |
(57)
VLD |
14:25-15:15 |
[Invited Talk]
Efficient LSI design enablement by AI |
Masayuki Odagawa (Cadence Japan) |
| |
15:15-15:30 |
Break ( 15 min. ) |
Thu, Nov 14 PM
15:30 - 17:10 |
(58)
VLD |
15:30-15:55 |
|
|
(59)
VLD |
15:55-16:20 |
|
|
(60)
VLD |
16:20-16:45 |
|
() |
(61)
VLD |
16:45-17:10 |
|
|
: a
i
n-u