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Technical Committee on Dependable Computing (DC) (Searched in: 2009)
Search Results: Keywords 'from:2010-02-15 to:2010-02-15'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2010-02-15 09:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Statistical Method of Small Iddq Variance Outlier Detection Yoshiyuki Nakamura, Masashi Tanaka (NEC Electronics)  DC2009-65 |
With manufacturing process advances, Iddq test becomes difficult due to its variance. Though ?Iddq or various methods we... [more] | DC2009-65 pp.1-5 |
| DC | 2010-02-15 09:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Re-Ordering for Thermal-Uniformity during Test Makoto Nakao, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-66 |
Power consumption during VLSI testing varies spatially and temporally, and it leads to temperature variation during tes... [more] | DC2009-66 pp.7-12 |
| DC | 2010-02-15 10:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study on a Test Generation Method for Transition Faults Using Multi Cycle Capture Test Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2009-67 |
Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, i... [more] | DC2009-67 pp.13-18 |
| DC | 2010-02-15 10:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Modeling resistive open faults and generating their tests Hiroshi Takahashi, Yoshinobu Higami, Yuta Shudo, Yuji Takamune, Yuzo Takamatsu (Ehime Univ.), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2009-68 |
In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive ope... [more] | DC2009-68 pp.19-24 |
| DC | 2010-02-15 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Method of Reproducing Iuput/Ouput Error Trace on High-level Design for Hardware Debug Support Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto (Univ. of Tokyo.), Masahiro Fujita (Univ. of Tokyo./JST) DC2009-69 |
[more] | DC2009-69 pp.25-30 |
| DC | 2010-02-15 11:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A binding method for testability based on resources sequential depth reduction Takaaki Cho, Toshinori Hosokawa (Nihon Univ.) DC2009-70 |
Behavioral descriptions are recently used for circuit designs on application specific fields. Behavioral synthesis is us... [more] | DC2009-70 pp.31-38 |
| DC | 2010-02-15 13:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Reduction of execution times and areas for delay measurement by subtraction Toru Tanabe, Hirohisa Minato, Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) DC2009-71 |
Since VLSI is in nanoscase size, high density and high speed in recent years, small-delay defects which change propagati... [more] | DC2009-71 pp.39-44 |
| DC | 2010-02-15 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Compaction Oriented Control Point Insertion Method for Transition Faults Yoshitaka Yumoto, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.) DC2009-72 |
The recent advances in semiconductor processing technology have resulted in the exponential increase in LSI circuit dens... [more] | DC2009-72 pp.45-50 |
| DC | 2010-02-15 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | On Calculation of Delay Test Quality for Test Cubes and X-filling Shinji Oku, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech./JTS) DC2009-73 |
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns... [more] | DC2009-73 pp.51-56 |
| DC | 2010-02-15 14:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Seed Selection for High Quality Delay Fault Test in BIST Akira Taketani, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (Nara Inst. of Sci and Tech.) DC2009-74 |
In this paper, we target a scan BIST architecture that consists of LFSR, phase shifter and MISR, and propose a method to... [more] | DC2009-74 pp.57-62 |
| DC | 2010-02-15 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Acceptable Faults in Digital Filters Takumi Miyaguchi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2009-75 |
In this paper, we propose a method for distinguishing acceptable and unacceptable faults in digital filters. Analyzing t... [more] | DC2009-75 pp.63-68 |
| DC | 2010-02-15 15:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | High Speed X-Fault Diagnosis with Partial X-Resolution Kohei Miyase (Kyushu Inst. of Tech.), Yusuke Nakamura (Panasonic Communications Software Co.,Ltd.), Yuta Yamato, Xiaoqing Wen, Seiji Kajihara (Kyushu Inst. of Tech.) DC2009-76 |
Defects behavior of ultra small size and high speed LSI is getting complicated. It makes localization of fault site and ... [more] | DC2009-76 pp.69-74 |
| DC | 2010-02-15 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Consideration of Open Faults Model Based on Digital Measurement of TEG Chip Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77 |
Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. ... [more] | DC2009-77 pp.75-80 |
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