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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2016-12-16 13:00 |
Yamagata | Sakata Sogo-Bunka Center(Sakata-City) | High Reliable Memory Architecture with Adaptive Combination of Aging-Aware In-Field Self-Repair and ECC Gian Mayuga, Yuta Yamato (NAIST), Yasuo Sato (KIT), Michiko Inoue (NAIST)  DC2016-64 |
[more] | DC2016-64 pp.1-6 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 11:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD) VLD2016-67 DC2016-61 |
Due to outsourcing of numerous stages of the IC manufacturing process in different foundries, security risks such as har... [more] | VLD2016-67 DC2016-61 pp.135-140 |
| DC, SS | 2016-10-27 11:50 |
Shiga | Hikone Kinro-Fukushi Kaikan Bldg. | Faster Wait-free Randomized Consensus with an Oblivious Adversary for MRSW Register Model Sen Moriya (Kindai Univ.), Michiko Inoue (NAIST) SS2016-20 DC2016-22 |
We consider wait-free randomized consensus algorithms with an oblivious adversary in asynchronous shared-memory system u... [more] | SS2016-20 DC2016-22 pp.13-18 |
| COMP | 2016-09-06 11:00 |
Toyama | Toyama Prefectural University | Gathering of mobile agents in Byzantine environments with authenticated whiteboards Masashi Tsuchida, Fukuhito Ooshita, Michiko Inoue (NAIST) COMP2016-15 |
We propose an algorithm for the gathering problem of mobile agents in Byzantine environments. The proposed algorithm can... [more] | COMP2016-15 pp.7-14 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2016-03-25 15:45 |
Nagasaki | Fukue Bunka Hall/Rodou Fukushi Center | A consideration on variation correction for fail prediction in LSI test Ryo Ogawa (NAIST), Yoshiyuki Nakamura (Renesas Semiconductor Package & Test Solutions), Michiko Inoue (NAIST) CPSY2015-158 DC2015-112 |
Recently, a test cost reduction using data mining has been attracted. It is expected to reduce the cost by predicting fa... [more] | CPSY2015-158 DC2015-112 pp.271-276 |
| DC | 2016-02-17 11:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Delay fault injection framework based on logic simulation with zero delay model Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-90 |
Fault injection is a technique to re-create faulty behavior of circuits and widely accepted method to evaluate soft erro... [more] | DC2015-90 pp.25-30 |
| DC | 2016-02-17 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) DC2015-92 |
Built-In Self-Test (BIST) is widely used to reduce test cost. However, it is difficult to achieve high fault coverage wi... [more] | DC2015-92 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 12:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST) VLD2015-38 DC2015-34 |
Outsourcing of IC fabrication components has initiated the potential threat of design tempering using hardware Trojans ... [more] | VLD2015-38 DC2015-34 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-01 13:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) VLD2015-40 DC2015-36 |
The Neighborhood Pattern Sensitive Fault (NPSF) is widely discussed fault model for memories, and it occurs when a memor... [more] | VLD2015-40 DC2015-36 pp.19-24 |
| COMP | 2015-09-01 14:00 |
Nagano | A Silent Anonymous Self-Stabilizing Algorithm to Construct 1-Maximal Matching under the Distributed Daemon in Trees Yuma Asada, Fukuhito Ooshita, Michiko Inoue (NAIST) COMP2015-20 |
We propose a silent self-stabilizing 1-maximal matching algorithm for anonymous trees under a distributed unfair daemon.... [more] | COMP2015-20 pp.27-34 |
|
| DC | 2014-12-19 14:15 |
Toyama | Reliability of ECC-based Memory Architectures with Online Self-repair Capabilities Gian Mayuga, Yuta Yamato, Tomokazu Yoneda (NAIST), Yasuo Sato (Kyutech), Michiko Inoue (NAIST) DC2014-70 |
[more] | DC2014-70 pp.19-24 |
|
| DC | 2014-10-27 15:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Efficient Silent Self-Stabilizing Algorithm to Solve 1-Maximal Matching in Anonymous Networks Yuma Asada, Michiko Inoue (NAIST) DC2014-23 |
We propose a new self-stabilizing 1-maximal matching algorithm which is silent and works for any anonymous networks with... [more] | DC2014-23 pp.11-16 |
| COMP | 2014-03-10 14:15 |
Tokyo | Randomized consensus algorithm using MRSW registers under oblivious adversary Satoru Nakajima, Michiko Inoue (NAIST) COMP2013-68 |
In this paper, we propose an efficient randomized consensus algorithm in distributed shared register model under an obli... [more] | COMP2013-68 pp.53-60 |
|
| DC | 2013-12-13 13:00 |
Ishikawa | Efficient Scan-Based BIST Architecture for Application-Dependent FPGA Test Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue (NAIST) DC2013-68 |
This paper presents a scan-based BIST architecture for testing of application-dependent circuits configured on FPGA. I... [more] |
DC2013-68 pp.1-6 |
|
| DC | 2013-02-13 16:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Data volume reduction method for unknown value handling in built-in self test used in field Yuta Yoshimi (NAIST), Kazumi Hatayama, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue (NAIST/JST) DC2012-90 |
Many approaches on test pattern compression targeted unknown value handling. It is because unknown values have impacts o... [more] | DC2012-90 pp.61-66 |
| DC | 2012-06-22 16:10 |
Tokyo | Room B3-1 Kikai-Shinko-Kaikan Bldg | On Per-Cell Dynamic IR-Drop Estimation in At-Speed Scan Testing Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue (NAIST) DC2012-15 |
It is well known that dynamic IR-drop analysis consumes large amount of time even for a few clock cycles. This paper add... [more] | DC2012-15 pp.39-44 |
| DC | 2012-02-13 15:55 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dynamic Test Scheduling for In-Field Aging Detection Yosuke Morinaga, Tomokazu Yoneda (NAIST), Hyunbean Yi (Hanbat National Univ.), Michiko Inoue (NAIST) DC2011-85 |
[more] | DC2011-85 pp.55-60 |
| DC | 2011-02-14 11:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Pattern Generation Method to Uniform Initial Temperature of Test Application Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-63 |
Circuit failure prediction is essential to ensure product quality and in-field reliability. The basic principle of circu... [more] | DC2010-63 pp.27-32 |
| DC | 2011-02-14 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Test Pattern Generation for Highly Accurate Delay Testing Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) DC2010-64 |
We propose a new faster-than-at-speed test method to detect small delay defects. As semiconductor technology is scaling ... [more] | DC2010-64 pp.33-38 |
| ICD (Workshop) |
2010-08-16 - 2010-08-18 |
Overseas | Ho Chi Minh City University of Technology | [Invited Talk]
Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.) |
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more] | |
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