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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2008)
Search Results: Keywords 'from:2008-11-17 to:2008-11-17'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:25 |
Fukuoka | Kitakyushu Science and Research Park | Adaptive routing of the 2-D torus network based on a Turn model Kazuya Matoyama, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-43 |
[more] | RECONF2008-43 pp.27-32 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:50 |
Fukuoka | Kitakyushu Science and Research Park | Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology) RECONF2008-44 |
By progress of VLSI technology, "On-Chip-Multiprocessor" which processes in parallel on a wafer has been realized, and a... [more] | RECONF2008-44 pp.33-38 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 16:15 |
Fukuoka | Kitakyushu Science and Research Park | Soft Error Mitigation Techniques for FPGA Switch Matrices Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) RECONF2008-45 |
Recentry, a soft error becomes a serious probrem as the process shrinking. Especially, SRAMs seriously suffer from a sof... [more] | RECONF2008-45 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 16:40 |
Fukuoka | Kitakyushu Science and Research Park | Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation Wang Luzhou, Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto (Tohoku Univ.) RECONF2008-46 |
We propose array-structured custom-computing machines for high-performance difference scheme computation. The performanc... [more] | RECONF2008-46 pp.45-48 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:00 |
Fukuoka | Kitakyushu Science and Research Park | A Path-Based Thread Partitioning Technique Considering Loop Structures Hirohito Ogawa, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2008-37 |
Speed-up by the multithreaded execution is important to make use of the performance of the multi-core processor effect... [more] |
CPSY2008-37 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:25 |
Fukuoka | Kitakyushu Science and Research Park | Program Behavior Analysis Based on Loop Paths Hideto Yanome, Kanemitsu Ootsu, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2008-38 |
The well-known 90/10 locality rule indicates that a program executes about 90% of its instructions using only 10% of its... [more] | CPSY2008-38 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:50 |
Fukuoka | Kitakyushu Science and Research Park | Initial Examination of Detour Routing that uses Global Information Hiroki Mori, Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba (Utsunomiya Univ.) CPSY2008-39 |
Recently, massively parallel computers with many nodes appears. They aim at achieving high performance by increasing of ... [more] | CPSY2008-39 pp.13-18 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 12:35 |
Fukuoka | Kitakyushu Science and Research Park | Decoded Instruction Cache for Server Virtualization Feature Toshiomi Moriki, Naoya Hattori, Yuji Tsushima, Eiichiro Oiwa (Hitachi, Ltd., Central Research Laboratory) CPSY2008-40 |
[more] | CPSY2008-40 pp.19-24 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:00 |
Fukuoka | Kitakyushu Science and Research Park | Memory Virtualization Mechanism for Server Virtualization Naoya Hattori, Toshiomi Moriki, Yuji Tsushima, Norimitsu Hayakawa (Hitachi, ltd) CPSY2008-41 |
Complexity of IT system brings TCO increase. To reduce TCO of IT systems, server consolidation via virtualization techno... [more] | CPSY2008-41 pp.25-30 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka | Kitakyushu Science and Research Park | An optimization method for MIMD controlled data communication of MX Core Akihiro Kodama, Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2008-42 |
The massively parallel SIMD (Single Instruction Multiple Data) processor MX Core, which has been developed by Renesas te... [more] | CPSY2008-42 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka | Kitakyushu Science and Research Park | A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-76 DC2008-44 |
In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its ... [more] | VLD2008-76 DC2008-44 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | Evaluation of Hardware Algorithms on a Circuit Model Considering Wire Delay Tetsuya Nagase, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) VLD2008-77 DC2008-45 |
In the design of integrated circuits, it is important to design or choose algorithms according to the requirements such ... [more] | VLD2008-77 DC2008-45 pp.103-108 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:00 |
Fukuoka | Kitakyushu Science and Research Park | Improving the Accuracy of Rule-based Equivalence Checking of High-level Desciptions by Identifying Potential Internal Equivalences Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo) |
Rule-based equivalence checking of high-level design descriptions proves the equivalence of two high-level design descri... [more] | VLD2008-78 DC2008-46 pp.109-114 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 13:25 |
Fukuoka | Kitakyushu Science and Research Park | Generation of High Coverage Property Set Using Counterexamples Takeshi Matsumoto, Yeonbok Lee, Hiroaki Yoshida (Univ. of Tokyo), Hisashi Yomiya (Toshiba Corporation), Masahiro Fujita (Univ. of Tokyo) |
[more] | VLD2008-79 DC2008-47 pp.115-120 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:30 |
Fukuoka | Kitakyushu Science and Research Park | [Poster Presentation]
A Test Point Insertion Method for Test Data Reduction Based on Necessary Assignment Kazuko Hiramoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ) VLD2008-80 DC2008-48 |
In this work, we discuss a method for reducing test data by test point insertion. Focusing on the fact that test points ... [more] | VLD2008-80 DC2008-48 pp.121-126 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 10:55 |
Fukuoka | Kitakyushu Science and Research Park | [Poster Presentation]
A Hybrid Delay Scan forDelay Testing Based on Propagation Dominance Tomomi Nuwa, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2008-81 DC2008-49 |
The hybrid delay scan design [1], where part of FFs can be controlled as skewed-load ones, is an effective method for a... [more] |
VLD2008-81 DC2008-49 pp.127-132 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 11:20 |
Fukuoka | Kitakyushu Science and Research Park | A Reconfigurable Wrapper Design for Testing Cores with Multi-Clock Domains Takashi Yoshida, Tomokazu Yoneda, Hideo Fujiwara (Nara Institute of Science and Technology) VLD2008-82 DC2008-50 |
This paper presents an optimization method for designing reconfigurable test wrappers for cores with multiple clock doma... [more] | VLD2008-82 DC2008-50 pp.133-138 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 09:00 |
Fukuoka | Kitakyushu Science and Research Park | [Invited Talk]
The End of Moore`s Law and the Future of Computing Systems, Probably Krishna V. Palem (Rice Univ.) RECONF2008-47 |
Many claim that the laws of physics dictating the exponentially improving benefits of Moore's Law will end in the next... [more] |
RECONF2008-47 p.49 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-18 09:50 |
Fukuoka | Kitakyushu Science and Research Park | [Invited Talk]
C-based Programmable-HW Core "STP Engine": Current Status and the Future Masato Motomura (NEC Electronics) RECONF2008-48 |
[more] | RECONF2008-48 pp.51-56 |
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