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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2017-04-21 11:25 |
Tokyo | [Invited Lecture]
A 2x Logic Density Programmable Logic Array using Atom Switch Yukihide Tsuji, Xu Bai, Ayuka Morioka, Miyamura Makoto, Ryusuke Nebashi, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada, Tadahiko Sugibayashi (NEC)  ICD2017-14 |
(To be available after the conference date) [more] | ICD2017-14 pp.73-78 |
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| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 10:30 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Area-efficient LUT-like Programmable Logic Using Atom Switch and its Delay-optimal Mapping Algorithm Toshiki Higashi, Hiroyuki Ochi (Ritsumeikan Univ.) RECONF2016-45 |
This paper proposes a delay model for 0-1-$A$-$overline{A}$ LUT and a delay-optimal mapping algorithm for it. 0-1-$A$-$o... [more] | RECONF2016-45 pp.29-34 |
| RECONF | 2014-06-12 10:50 |
Miyagi | Katahira Sakura Hall | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] | RECONF2014-6 pp.27-30 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-08 10:35 |
Aomori | New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57 |
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] | VLD2013-57 ICD2013-81 IE2013-57 pp.59-64 |
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| SDM, ICD | 2013-08-02 13:00 |
Ishikawa | Kanazawa University | A 0.4-1V SAR ADC Using Wide Range Operation Asynchronous Controller Yosuke Toyama, Akira Shikata, Kentaro Yoshioka, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ.) SDM2013-80 ICD2013-62 |
This paper presents a wide range in supply voltage, resolution, and sampling rate asynchronous successive approximation ... [more] | SDM2013-80 ICD2013-62 pp.77-82 |
| VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2012-01-26 16:40 |
Kanagawa | Hiyoshi Campus, Keio University | Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) VLD2011-119 CPSY2011-82 RECONF2011-78 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | VLD2011-119 CPSY2011-82 RECONF2011-78 pp.163-168 |
| RECONF | 2011-09-27 13:20 |
Aichi | Nagoya Univ. | Design and Implementation of Adaptive Viterbi Decoder using Dynamic Reconfigurable System STP Engine Yuken Kishimoto, Takao Toi, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2011-38 |
Implementing Viterbi Algorithm that is the decoding method of Convolutional code on hard-wired logic, in order to variou... [more] | RECONF2011-38 pp.93-98 |
| SDM, ICD | 2011-08-25 09:50 |
Toyama | Toyama kenminkaikan | Study of pattern area for reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) SDM2011-73 ICD2011-41 |
Pattern area for 2~6 input reconfigurable logic circuit with double-gate (DG), Carbon-Nano-Tube (CNT), double-gate and C... [more] | SDM2011-73 ICD2011-41 pp.13-16 |
| SCE | 2010-10-19 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Demonstration of a 2x2 Single-Flux-Quantum Reconfigurable Data-Path Based on the 10-kA/cm2 Process Masakazu Okada, Irina Kataeva, Masato Ito, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Shuuichi Nagasawa (ISTEC), Naofumi Takagi (Kyoto Univ.) SCE2010-33 |
We have demonstrated a reconfigurable data-path (RDP) prototype using the single-flux-quantum (SFQ) circuits fabricated ... [more] | SCE2010-33 pp.55-60 |
| RECONF | 2010-09-17 09:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | COGRE: A Novel Compact Logic Cell Architecture for Area Reduction Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-31 |
In order to implement logic functions, conventional field programmable gate arrays (FPGAs) adopt look-up tables (LUTs) a... [more] | RECONF2010-31 pp.79-84 |
| ICD, SDM | 2010-08-27 15:10 |
Hokkaido | Sapporo Center for Gender Equality | Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor Takamichi Hayashi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2010-148 ICD2010-63 |
Reconfigurable logic for more than 3input based on MOS double gate / Carbon Nano Tube transistor has been newly proposed... [more] | SDM2010-148 ICD2010-63 pp.131-136 |
| RECONF | 2010-05-13 15:20 |
Nagasaki | First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.) RECONF2010-5 |
An advantage of a RLD such as an FPGA is that it can be customized after being manufactured. However, there is a problem... [more] | RECONF2010-5 pp.25-30 |
|
| ED, SDM | 2010-02-23 11:00 |
Okinawa | Okinawaken-Seinen-Kaikan | Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network Yuta Shiratori, Kensuke Miura (Hokkaido Univ.), Seiya Kasai (Hokkaido Univ./JST) ED2009-208 SDM2009-205 |
We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon’s expansion of Boolean logic functio... [more] | ED2009-208 SDM2009-205 pp.71-76 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 10:15 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Evaluation using Applications for RC-OS which supports Reconfigurable Computer System Kazuya Tokunaga, Akira Kojima, Tetsuo Hironaka (Hiroshima City Univ) VLD2009-72 CPSY2009-54 RECONF2009-57 |
FPGAs which allow users to create arbitrary logic circuits are used for speedup of the processing in many fields. We hav... [more] | VLD2009-72 CPSY2009-54 RECONF2009-57 pp.19-24 |
| SCE | 2009-10-20 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dynamically Reconfigurable Single Flux Quantum Logic Gates Yuki Yamanashi, Ichiro Okawa, Nobuyuki Yoshikawa (Yokohama Nat. Univ.) SCE2009-20 |
Novel reconfigurable superconductive single flux quantum logic gates, the function of which can be dynamically defined b... [more] | SCE2009-20 pp.19-23 |
| SIS | 2009-03-05 15:45 |
Tokyo | [Special Talk]
System Realizations by Using Embedded Memories in FPGAs Yukihiro Iguchi (Meiji Univ.) |
FPGAs (Field Programmable Gate Arrays) have many embedded RAMs. We can use them for register files, FIFO (First In, Fi... [more] |
SIS2008-80 pp.49-54 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 15:10 |
Kanagawa | A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) VLD2008-121 CPSY2008-83 RECONF2008-85 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | VLD2008-121 CPSY2008-83 RECONF2008-85 pp.177-182 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:00 |
Fukuoka | Kitakyushu Science and Research Park | A Study of Local Interconnect Architecture for Variable Grain Logic Cell Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42 |
Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic l... [more] | RECONF2008-42 pp.21-26 |
| SCE | 2008-10-30 14:50 |
Ibaraki | AIST | Demonstration of a Single-Flux-Quantum Floating-Point Divider for the Reconfigurable Data-path Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2008-27 |
We report implementation and experimental results of a single-flux-quantum (SFQ) floating-point serial divider developed... [more] | SCE2008-27 pp.29-34 |
| RECONF | 2008-09-26 10:30 |
Okayama | Okayama Univ. | Exploration of Input Granularity Optimization for Variable Grain Logic Cell Masahiro Koga, Hiroshi Miura, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-33 |
A Reconfigurable Logic Device (RLD), which has circuit programmability, is applied to embedded systems as a hardware Int... [more] | RECONF2008-33 pp.63-68 |
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