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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS | 2024-04-19 17:15 |
Tokyo | (Primary: On-site, Secondary: Online) |
Supply chain security of semiconductor chips and countermeasure design technologies Makoto Nagata (Kobe Univ.), Kazuki Monta (Secafy Co., Ltd.), Yuichi Hayashi (NAIST), Naofumi Homma (Tohoku Univ.)  HWS2024-7 |
This report is dedicated to the threats and countermeasures of semiconductor supply chain security, regarding the authen... [more] | HWS2024-7 pp.30-33 |
| ICD | 2024-04-12 10:45 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Talk]
Recent Developments and Challenges for NAND Flash Memory Interface Takashi Toi (KIOXIA) ICD2024-11 |
(To be available after the conference date) [more] | ICD2024-11 p.36 |
| RCS, SR, SRW (Joint) |
2024-03-13 11:30 |
Tokyo | The University of Tokyo (Hongo Campus), and online (Primary: On-site, Secondary: Online) |
[Technology Exhibit]
A Study of Edge AI & Distributed DB Computing Technology for Edge AI Digital Twin
-- Cyber Brain Module -- Hiroshi Miyata (TAN), Kazutami Arimoto (Okayama Prf. Univ.), Atsushi Hayami, Hisayoshi Mizuno (TAN), Tomoyuki Yokogawa (Okayama Prf. Univ.) RCS2023-253 |
After 5G, the realization of the edge digital twin, which integrates sensor data from edge terminals, has become a reali... [more] | RCS2023-253 pp.17-22 |
| VLD, HWS, ICD | 2024-02-29 11:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Study of Edge AI & Distributed DB Computing Architecture for Edge-Centric Digital Twin Hiroshi Miyata (TAN), Kazutami Arimoto (Okayama Pref. Univ.), Atsushi Hayami, Hisayoshi Mizuno (TAN), Tomoyuki Yokogawa (Okayama Pref. Univ.) VLD2023-111 HWS2023-71 ICD2023-100 |
After 5G, the realization of the edge digital twin, which integrates sensor data from edge terminals, has become a reali... [more] | VLD2023-111 HWS2023-71 ICD2023-100 pp.72-76 |
| SANE | 2023-12-08 15:50 |
Overseas | Surakarta, Indonesia (Primary: On-site, Secondary: Online) |
High Gain 3 Stages RF Power Amplifier S-Band Radar Elyas Palantei, Regita Pramestia Nanang Muh Nawir, Dewiani, Zulfahmi Rizal (UNHAS), Josaphat Tetuko Sri Sumantyo (Chiba Univ.), Josaphat Tetuko Sri Sumantyo (UNS) |
The construction of modern reconfigurable radar technology to flexible in frequency operation and has an accurate sensin... [more] | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-15 14:40 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo) VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 |
A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the... [more] | VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 pp.54-59 |
| LQE, OPE, CPM, EMD, R | 2023-08-24 16:40 |
Miyagi | Tohoku university (Primary: On-site, Secondary: Online) |
[Invited Talk]
Failure Mode and Analytical Method for Chip Components
-- Analysis Example and Correspondence to Miniaturization -- Akira Saito (Murata) R2023-25 EMD2023-20 CPM2023-30 OPE2023-69 LQE2023-16 |
Higher reliability of electric components is demanded with the evolution of AI and the automatic driving. Electric chara... [more] | R2023-25 EMD2023-20 CPM2023-30 OPE2023-69 LQE2023-16 pp.45-50 |
| EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] | 2023-07-25 11:20 |
Hokkaido | Hokkaido Jichiro Kaikan | Secure Cryptographic Unit with built-in Signature Generation Hardware for Aggregate Signature Schemes and its FPGA Implementation Toshihiro Sato, Shohei Kawasaki (SCU), Kaoru Masada (Tokyo Univ.), Riku Anzai, Junichi Sakamoto, Naoki Yoshida (YNU), Yasuyoshi Uemura (SCU), Makoto Ikeda (Tokyo Univ.), Tsutomu Matsumoto (YNU) ISEC2023-42 SITE2023-36 BioX2023-45 HWS2023-42 ICSS2023-39 EMM2023-42 |
Secure Cryptographic Unit (SCU) consists of a hardware cryptographic engine and an access control mechanism for the engi... [more] | ISEC2023-42 SITE2023-36 BioX2023-45 HWS2023-42 ICSS2023-39 EMM2023-42 pp.182-187 |
| ICD | 2023-04-10 16:05 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
Strong PUF Using SRAM Weak PUF-Based Secret Substitution Layer for Edge-Device Security Applications Kunyang Liu, Hirofumi Shinohara (Waseda Univ.) ICD2023-7 |
Strong physically unclonable function (PUF) provides a promising solution for lightweight security applications aimed at... [more] | ICD2023-7 p.15 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2022-11-28 13:05 |
Kumamoto | (Primary: On-site, Secondary: Online) |
Development of ASIC Prototype Chip Evaluation System using FPGA-SoM Masashi Imai (Hirosaki Univ.), Kenji Kise (Tokyo Tech.), Tomohiro Yoneda (NII) VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 |
An ASIC prototype chip requires the corresponding evaluation system based on its specification, resulting in lack of ver... [more] | VLD2022-19 ICD2022-36 DC2022-35 RECONF2022-42 pp.1-6 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 14:50 |
Online | Online | Implementation of a RISC-V SMT Core in Virtual Engine Architecture Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT) VLD2021-57 CPSY2021-26 RECONF2021-65 |
The RISC-V core which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture has been... [more] | VLD2021-57 CPSY2021-26 RECONF2021-65 pp.43-48 |
| MW | 2021-12-16 15:40 |
Kanagawa | Kawasaki City Industrial Promotion Hall (Primary: On-site, Secondary: Online) |
Series-Series Feedback D-band CMOS Amplifier using a Radial Stub for Source Grounding Taiki Machii (Tohoku Univ.), Mizuki Motoyoshi (SIST), Suguru Kameda (Hiroshima Univ.), Noriharu Suematsu (Tohoku Univ.) MW2021-93 |
Positive feedback is effective to improve the gain since sufficient gain cannot be achieved with over-100 GHz CMOS ampli... [more] | MW2021-93 pp.49-54 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei, Takuya Kojima, Hideharu Amano (Keio Univ.), Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami (SIT), Keizo Hiraga, Kenta Suzuki (SSS) VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 |
IoT and edge-computing have been attracting much attention and demands for power efficiency as well as high performance ... [more] | VLD2021-20 ICD2021-30 DC2021-26 RECONF2021-28 pp.19-24 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:35 |
Online | Online | Basic evaluation of ReNA, a DNN accelerator using numerical representation posit Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 |
In Convolutional Neural Network (CNN) accelerators for edge, numerical precision of data should be reduced as much as po... [more] | VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32 pp.43-48 |
| MW | 2021-11-18 13:05 |
Kagoshima | Kagoshima University (Primary: On-site, Secondary: Online) |
4-way Power Combiner Including Board-to-Board Transition Using Spring Contact Probes Takuma Nishimura, Hidenori Ishibashi, Yutarou Yamaguchi, Takumi Nagamine, Hidenori Yukawa, Toru Fukasawa, Yoshio Inasawa (MELCO) MW2021-66 |
Conventional SSPA has a method of synthesizing power by mounting multiple MMIC on the board with flip-chip bonding for h... [more] | MW2021-66 pp.1-6 |
| RECONF | 2021-06-08 16:10 |
Online | Online | Automatic generation of executable code for ReNA Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) RECONF2021-6 |
We have been developing ReNA as a CNN accelerator for the edge, which is controlled by directly specifying control signa... [more] | RECONF2021-6 pp.26-31 |
| WBS, IT, ISEC | 2021-03-04 10:15 |
Online | Online | Error Performances of Synchronous Optical Code-Division Multiple Access Schemes Using Chip-Pair Codes Tomoko K. Matsushima, Shoichiro Yamasaki, Kyohei Ono (Polytechnic Univ.) IT2020-114 ISEC2020-44 WBS2020-33 |
This paper investigates the bit error rate performance of synchronous optical code-division multiple access (CDMA) using... [more] | IT2020-114 ISEC2020-44 WBS2020-33 pp.13-18 |
| IT | 2020-12-03 14:50 |
Online | Online | A Study on Signature Codes for Synchronous Optical CDMA Systems
-- Proposal of Shortened Codes Based on Generalized Modified Prime Sequence Codes -- Kyohei Ono, Shoichiro Yamasaki, Tomoko K. Matsushima (Polytechnic Univ.) IT2020-57 |
In this paper, we propose a class of new spreading codes for synchronous optical CDMA and introduce a construction metho... [more] | IT2020-57 pp.177-182 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-17 10:45 |
Online | Online | Implementation of YOLO in the AI accelerator ReNA Toma Uemura, Yasuhiro Nakahara, Motoki Amagasaki, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) VLD2020-22 ICD2020-42 DC2020-42 RECONF2020-41 |
The object detection，which is a typical AI process，has been attracting attention in various fields because it can identi... [more] | VLD2020-22 ICD2020-42 DC2020-42 RECONF2020-41 pp.66-71 |
| OFT | 2020-10-09 14:30 |
Online | Online | Interferometer based on photonic integrated circuit for optical frequency domain reflectometry Victor Shishkin, Akio Higo, Hideaki Murayama (UTokyo) OFT2020-34 |
We demonstrate an ultra-compact interferometer integrated on silicon photonic chip for distributed sensing using optical... [more] | OFT2020-34 pp.109-111 |
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