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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2019-02-28 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)  VLD2018-108 HWS2018-71 |
In recent years, IoT devices are rapidly increasing. One of the IoT devices is a sensor node and a small medical device... [more] | VLD2018-108 HWS2018-71 pp.91-96 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 14:55 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control Yusuke Yoshida, Kimiyoshi Usami (SIT) VLD2017-33 DC2017-39 |
Embedded memory macros are major central building blocks of any microprocessor and greatly affect power dissipation. In ... [more] | VLD2017-33 DC2017-39 pp.37-42 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:25 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Ultra Low Power Reconfigurable Accelerator CC-SOTB2 Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2016-54 DC2016-48 |
Cool mega array (CMA) is a low power coarse-grained reconfigurable accelerator developed using silicon on thin BOX (SOTB... [more] | VLD2016-54 DC2016-48 pp.61-66 |
| ICD, SDM, ITE-IST [detail] | 2016-08-03 14:15 |
Osaka | Central Electric Club | Impacts of Flexible V_th control and Low Process Variability of SOTB to Ultra-low Voltage Designs Yasuhiro Ogasahara (AIST) SDM2016-65 ICD2016-33 |
This paper discusses impacts of flexible Vth control, low process variability, and steep SS with small on-current of new... [more] | SDM2016-65 ICD2016-33 pp.111-116 |
| VLD | 2016-03-01 17:05 |
Okinawa | Okinawa Seinen Kaikan | Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) VLD2015-130 |
In recent years, energy harvesting and sensor node have attracted a lot of attention. Therefore, a memory which can redu... [more] | VLD2015-130 pp.111-116 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 10:55 |
Kanagawa | Hiyoshi Campus, Keio University | Power Reduction of TLB using Body Bias Control on SOTB Daiki Kawase, Hayate Okuhara, Hideharu Amano (Keio Univ.) VLD2015-102 CPSY2015-134 RECONF2015-84 |
SOTB(Silicon on thin buried oxide) MOSFET is one of the FD-SOI device with 10nm BOX layer. SOTB effectively reduces the... [more] |
VLD2015-102 CPSY2015-134 RECONF2015-84 pp.191-196 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 17:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | The adaptive body bias generator for achieving the ultra-low power operation of the logic circuit Tomoaki Koide, Kouichirou Ishibashi (UEC), Nobuyuki Sugi (LEAP) CPM2015-134 ICD2015-59 |
The leakage has been increasing by miniaturization of the transistor in recently year. Adaptive body bias generator with... [more] | CPM2015-134 ICD2015-59 pp.39-43 |
| RECONF | 2015-06-20 14:00 |
Kyoto | Kyoto University | On the Evaluation Board AISTino equipped with the Fourth Flex Power FPGA chip with SOTB transistors Hanpei Koike, Masakazu Hioki, Yasuhiro Ogasahara (AIST), Hayato Ishigaki, Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa (AIST) RECONF2015-22 |
Flex Power FPGA utilizes threshold voltage programmability to reduce its static power by the body bias control of circui... [more] | RECONF2015-22 pp.119-124 |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 08:30 |
Kagoshima | Power optimization of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano (Keio Univ.) CPSY2014-174 DC2014-100 |
(To be available after the conference date) [more] | CPSY2014-174 DC2014-100 pp.71-76 |
|
| RECONF | 2014-06-12 11:40 |
Miyagi | Katahira Sakura Hall | Body bias control of low-power reconfigurable accelerator CMA-SOTB Yu Fujita, Hongliang Su, Hideharu Amano (Keio univ.) RECONF2014-8 |
For low power yet high performance processing in battery driven devices, a coarse grained reconfigurable accelerator cal... [more] | RECONF2014-8 pp.37-42 |
| VLD | 2014-03-05 13:50 |
Okinawa | Okinawa Seinen Kaikan | Design methodology on Dynamic Multi-Vth control technique for Silicon on Thin Buried Oxide(SOTB) Tatsuki Saigusa, Kimiyoshi Usami (Shibaura Inst. of Tech) VLD2013-162 |
Silicon on thin BOX(SOTB) is one of FD-SOI device.It is possible to operate with ultra-low voltage of 0.4V and greatly c... [more] | VLD2013-162 pp.153-158 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-16 17:00 |
Kanagawa | Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB) Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2012-120 CPSY2012-69 RECONF2012-74 |
Silicon on thin BOX(SOTB) is an FD-SOI device being possible to operate with ultra-low voltage of 0.4V and greatly chang... [more] | VLD2012-120 CPSY2012-69 RECONF2012-74 pp.75-80 |
|
| VLD | 2012-03-07 16:05 |
Oita | B-con Plaza | Leakage Energy Reduction of Sub-Threshold Circuits by Body Bias Control for Power Switch Ryo Mitsuhashi, Masaru Kudo, Yuya Ohta, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-144 |
Power Gating (PG) is one of the technologies for reducing leakage energy. The effectiveness of leakage energy reduction ... [more] | VLD2011-144 pp.145-150 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Sleep Depth Controlling for Run-Time Leakage Power Saving Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura (Tokyo Univ.) ICD2011-114 |
Since process technology has been in deep sub-micron era, leakage power dissipation is one of major concerns, and its re... [more] | ICD2011-114 p.69 |
|
| ICD, ITE-IST | 2011-07-21 09:55 |
Hiroshima | Hiroshima Institute of Technology | A Sense Amplifier with High Speed Pre-Charge Operation for Ultra-Low-Voltage SRAM Chotaro Masuda, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kove Univ.) ICD2011-22 |
We propose a current latch sense amplifier with a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is capable of hig... [more] |
ICD2011-22 pp.7-12 |
| VLD | 2009-03-13 10:40 |
Okinawa | Layout Aware Cell Clustering for Body Biasing Koichi Hamamoto (Osaka Univ.), Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-159 |
Body bias control has been widely studied for performance compensation. In order to reduce leakage increase involved by ... [more] | VLD2008-159 pp.195-200 |
|
| VLD, CAS, SIP | 2008-06-26 15:05 |
Hokkaido | Hokkaido Univ. | An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ.) CAS2008-14 VLD2008-27 SIP2008-48 |
Body-biasing is expected to be a common design technique, then area efficient implementation in layout has been demanded... [more] | CAS2008-14 VLD2008-27 SIP2008-48 pp.75-79 |
| ICD | 2008-04-17 10:15 |
Tokyo | [Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] | ICD2008-2 pp.7-12 |
|
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-16 10:15 |
Kanagawa | Hiyoshi Campus, Keio University | [Invited Talk]
Flex Power FPGA Hanpei Koike (AIST) |
We have investigated Flex Power FPGA, in which fine-grain reconfigurable threshold voltage control enables substantial r... [more] | VLD2007-105 CPSY2007-48 RECONF2007-51 pp.1-6 |
| RECONF | 2006-05-18 14:15 |
Miyagi | TOHOKU UNIVERSITY | Detail Analysis of Optimal Body Bias Voltage Set for Flex Power FPGA Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) |
The Flex Power FPGA is a new FPGA architecture which enabled high speed operation and low power-consumption by controlli... [more] | RECONF2006-4 pp.19-24 |
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