Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2008-126
Optimum Code Scheduling for VLIW DSP SPXK5 considering Conditional Execution
Tetsuya Yamamoto, Nagisa Ishiura (Kwansei Gakuin Univ.), Takahiro Kumura, Masao Ikekawa (NEC), Masaharu Imai (Osaka Univ.)
pp. 1 - 6
VLD2008-127
Random Testing for Arithmetic Optimization of C compilers
Hironobu Awazu, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 7 - 10
VLD2008-128
Execution Trace Mining for Intratask DVFS in Embedded Systems
Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.)
pp. 11 - 16
VLD2008-129
[Invited Talk]
Model-Based Development for automotive control systems
-- Modeling Technique of microcontroller --
Yasuo Sugure, Shigeru Oho (Hitachi Ltd.)
pp. 17 - 22
VLD2008-130
Adjustable Safe Clocking and Relevant Register Assignment in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 23 - 28
VLD2008-131
Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.)
pp. 29 - 34
VLD2008-132
Fault Tolerant Datapath Synthesis Starting with Triple Algorithm Redundancy
Yutaka Tsuboishi, Mineo Kaneko (JAIST)
pp. 35 - 40
VLD2008-133
On the Minimization of Input Variables for Incompletely Specified Index Generation Functions
Takaaki Nakamura, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.)
pp. 41 - 46
VLD2008-134
A Lower Cost Clock Tree Synthesis Method in General-Synchronous Framework using an EDA tool
Hiroyoshi Hashimoto, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 47 - 52
VLD2008-135
A Delay Insertion Method for Clock Period Reduction with Fewer Delay Insertion in General-Synchronous Circuits
Shuhei Tani, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 53 - 58
VLD2008-136
A Maximization Method of Parallel Wire Lengths in Routing Area With Lengths in Routing Area with Obstacles
Suguru Suehiro, Yukihide Kohira, Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 59 - 64
VLD2008-137
Fast Optimization on Minimum Perturbation Placement Realization
Yuki Kouno, Yasuhiro Takashima (The Univ. of Kitakyushu), Atsushi Takahashi (Tokyo Inst. of Tech.)
pp. 65 - 70
VLD2008-138
Delay Estimation of Sub-path under Path-delay Test
Takanobu Shiki, Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC Corp.)
pp. 71 - 75
VLD2008-139
Chip evaluation and implimentation of DES encryption using via-programmable-device VPEX
Masahide Kawarasaki, Tomohiro Nishimoto, Yuuichi Kokushou, Kazuma Kitamura, Shouta Yamada (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyou Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 77 - 82
VLD2008-140
The implementation of DES cryptographic circuit and the evaluation of DPA attack resistance using Domino-RSL technique
Kenji Kojima, Kazuki Okuyama, Yuki Makino, Takeshi Fujino (Ritsumeikandai Univ.)
pp. 83 - 88
VLD2008-141
Differential Power Analysis of bit-value against cipher implementation on FPGA
Kazuki Okuyama, Kenji Kojima, Yuki Makino, Takeshi Fujino (Ritsumei Univ.)
pp. 89 - 94
VLD2008-142
A Formal Verification Method for On-Chip Programmable Interconnect
Takaaki Tagawa, Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo)
pp. 95 - 100
VLD2008-143
High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit
Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT)
pp. 101 - 106
VLD2008-144
A memory-reduction method for multi-rate LDPC encoder
Wenming Tang, Xianghui WEI, Satoshi Goto (Waseda Univ.)
pp. 107 - 110
VLD2008-145
Emulation of Sequential Circuits by a Parallel Branching Program Machine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.), Yoshifumi Kawamura (Renesas Technology Corp.)
pp. 111 - 116
VLD2008-146
A Proposal of an Adaptive Network on Chip for Multi-Core SoC
Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ)
pp. 117 - 122
VLD2008-147
A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC
Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST)
pp. 123 - 128
VLD2008-148
Automatic generation of Network-on-Chip topology under link length and latency constraint
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST)
pp. 129 - 134
VLD2008-149
A ring segmented bus architrcture for Globally Asynchronous Locally Synchronous System
Masafumi Kondo, Yoichiro Sato (Okayama Prefectural Univ), Kazuyuki Tashiro (FUJITSU TEN), Tomoyuki Yokogawa, Michiyoshi Hayase (Okayama Prefectural Univ)
pp. 135 - 140
VLD2008-150
Formal verification of GALS system designs using UPPAAL
Kazuaki Kirita, Tomoyuki Yokogawa, Hisashi Miyazaki, Yoichiro Sato, Michiyoshi Hayase (Okayama Pref. Univ.)
pp. 141 - 146
VLD2008-151
A Task Mapping Algorithm for Task Chaining Network Processor by Backtracking
Keita Saito, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 147 - 152
VLD2008-152
Delay Reduction Algorithm by Balancing Distribution of Traffic for Odd-Even Turn Model in NoCs
Shingo Wakita, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 153 - 158
VLD2008-153
Low Power Deblocking Filter Implementation Method for H.264/AVC
Yoshinori Hayashi, Tomohiro Akita, Tian Song, Takashi Shimamoto (Tokushima Univ.)
pp. 159 - 164
VLD2008-154
Transform and Quantization Architecture with All-Zero Detection and Bit Estimation for H.264/AVC
Hiroki Kuniyasu, Tomoyuki Kishida, Tian Song, Takashi Shimamoto (Tokushima Univ.)
pp. 165 - 170
VLD2008-155
Asynchronous $\pm2^k$ Gray-Code Adder
Shinya Matsuyama, Takashi Hisakado (Kyoto Univ.)
pp. 171 - 176
VLD2008-156
An algorithm for building RTL library
Masato Kawai, Hirofumi Kawauchi, Toshio Morikawa, Masaaki Ohtsuki, Masahiro Fukui (Ritsumeikan Univ.)
pp. 177 - 182
VLD2008-157
A Battery Charge/Discharge Simulator Close to Actual Behavior
Sayaka Iwakoshi, Keita Kojima, Kazunori Toi, Masahiro Fukui (Ritsumeikan Univ.)
pp. 183 - 188
VLD2008-158
A Study for Power Grid Simulator by using GPU
Hisako Sugano, Shinichi Nishizawa, Taiki Hashizume, Masahiro Fukui (Ritsumeikan Univ.)
pp. 189 - 194
VLD2008-159
Layout Aware Cell Clustering for Body Biasing
Koichi Hamamoto (Osaka Univ.), Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST)
pp. 195 - 200
VLD2008-160
Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits
Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST)
pp. 201 - 206
VLD2008-161
Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis
Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. of Tech.)
pp. 207 - 212
VLD2008-162
Implementation and performance measurement of low-power multiplier applying Run Time Power Gating
Mitsutaka Nakata, Toshiaki Shirai (Shibaura Inst. of Tech.), Seidai Takeda (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 213 - 218
VLD2008-163
Physical design and Evaluation of On-chip Leakage Monitor at 65nm devices
Satoshi Koyama, Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 219 - 224
VLD2008-164
Performance Evaluations of nMOS Level Shifter Circuits
Makoto Otsu, Shuji Tsukiyama (Chuo Univ.), Isao Shirakawa (Univ. of Hyogo), Shuji Nishi, Tomoyuki Nagai, Yasushi Kubota (Sharp Corp.)
pp. 225 - 230
VLD2008-165
Performance Evaluations of Two Measures for Statistical Design
Yuki Yoshida, Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.)
pp. 231 - 236
VLD2008-166
Study of high-speed low-power system LSI for sub-threshold operation
Makoto Tsurukubo, Shigeyoshi Watanabe (Shonan Inst. of Tech Graduate school)
pp. 237 - 241
VLD2008-167
Reduced pattern area technology of 3D transistor for system LSI
Yu Hiroshima, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 243 - 248
VLD2008-168
Examination of Low-power system LSI architecture by scheduling algorithm
Yoshikazu Sato, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 249 - 254
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.