Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2014] | [2015] | [2016] | [2017] | [2018] | [2019] | [2020] | [Japanese] / [English]
DC2017-33
hCODE 2.0: An Open-source Platform for FPGA Cluster System
Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 1 - 6
DC2017-34
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.)
pp. 7 - 12
DC2017-35
Considerations of Inside Structures for Approximate Multipliers
Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
pp. 13 - 18
DC2017-36
Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves
Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.)
pp. 19 - 24
DC2017-37
An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores
Hashidate Hidemi, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (Kyoto Sangyo Univ.)
pp. 25 - 30
DC2017-38
Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure
Yasuhiro Ogasahara, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 31 - 35
DC2017-39
Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control
Yusuke Yoshida, Kimiyoshi Usami (SIT)
pp. 37 - 42
DC2017-40
A shared memory chip for twin-tower of chips
Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.)
pp. 43 - 48
DC2017-41
A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST
Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.)
pp. 49 - 54
DC2017-42
An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics)
pp. 55 - 60
DC2017-43
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation
Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 61 - 66
DC2017-44
Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch
Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 67 - 72
DC2017-45
Routing method considering programming constraint of reconfigurable device using via-switch crossbars
Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
pp. 73 - 78
DC2017-46
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit
Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
pp. 79 - 84
DC2017-47
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech)
pp. 85 - 90
DC2017-48
On Avoiding Test Data Corruption by Optimal Scan Chain Grouping
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD)
pp. 91 - 94
DC2017-49
On low power oriented test pattern compaction using SAT solver
Yusuke Matsunaga (Kyushu Univ.)
pp. 95 - 99
DC2017-50
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table
Yuji Shindo, Kenshu Seto, Hao San (TCU)
pp. 101 - 104
DC2017-51
A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication
Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.)
pp. 105 - 108
DC2017-52
Implementation and Optimization of Parallel Prefix Adder Using Majority Function
Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.)
pp. 109 - 114
DC2017-53
Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits
Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
pp. 115 - 120
DC2017-54
Stochastic logic circuit using static constant as coefficient without random number generator
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 121 - 124
DC2017-55
Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time
Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 125 - 130
DC2017-56
[Invited Talk]
Innovative Applications of Machine Learning in Lithography and DFM
Tetsuaki Matsunawa (Toshiba Memory)
p. 131
DC2017-57
*
Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 133 - 138
DC2017-58
*
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 139 - 144
DC2017-59
A Detection Method for Trojan Circuit inserted in Manufacturing Process
Yoshinobu Okuda, Masayoshi Yoshimura, Kohei Ohyama (Kyoto Sangyo Univ.)
pp. 145 - 150
DC2017-60
[Keynote Address]
Theory and applications of dynamical sparse modeling
Masaaki Nagahara (Univ. of Kitakyushu)
pp. 169 - 170
DC2017-61
A Packet Lookup Engine LSI with Automatic Rule Registration and Deletion Function
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.)
pp. 171 - 176
DC2017-62
Real-time coefficient optimization method for PAM-4 transmitter equalizer
Yosuke Iijima, Keigo Taya (NIT, Oyama college), Yasushi Yuminaka (Gunma Univ.)
pp. 177 - 182
DC2017-63
A General Model of Timing Correction by Temperature Dependent Clock Skew
Mineo Kaneko (JAIST)
pp. 183 - 188
DC2017-64
Application of blind watermarking method for secondary use on smart community
Yuta Ohno, Akira Niwa, Hiroaki Nishi (Keio Univ.)
pp. 191 - 196
DC2017-65
A Study on Target Pin-Pairs Selection for Set-Pair Routing
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.)
pp. 235 - 240
DC2017-66
Max Length and Length Difference Minimization for Set Pair Routing Problem with ILP
Shutaro Hara, Kunihiro Fujiyoshi (TUAT)
pp. 241 - 246
DC2017-67
An Efficient Search Method on Stacked Rectangular Dissections
Masaki Yokota, Kunihiro Fujiyoshi (TUAT)
pp. 247 - 252
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.