Online edition: ISSN 2432-6380
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RECONF2021-57
Study on a Correlation Controlling Method to Realize Correlation-used Calculations Sequentially in Stochastic Computing
Shu Zhang, Shigeru Yamashita (Ritsumeikan Univ.)
pp. 1 - 6
RECONF2021-58
Study on Reverse Converters for RNS moduli set {2^k,2^n+1,2^n-1} using Signed-Digit numbers
Takahiro Morii, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 7 - 12
RECONF2021-59
Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer
Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
pp. 13 - 18
RECONF2021-60
Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems
Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 19 - 24
RECONF2021-61
FPGA Implementation of Scalable Fully Coupled Annealing Processing Sysytem by Using Multi-chip Operation
Kaoru Yamamoto, Takayuki Kawahara (TUS)
pp. 25 - 30
RECONF2021-62
Multi-spin-flip method for Ising machines and its application
Tatsuhiko Shirai, Nozomu Tagawa (Waseda Univ.)
pp. 31 - 36
RECONF2021-63
[Invited Talk]
A Challenge of Research, Development, Manufacturing, and Marketing of Quantum Computing Control Systems
Takefumi Miyoshi (QuEL, Inc./e-trees.Japan, Inc./Osaka Univ.)
p. 37
RECONF2021-65
Implementation of a RISC-V SMT Core in Virtual Engine Architecture
Hidetaro Tanaka, Tomoaki Tanaka, Keita Nagaoka, Ryosuke Higashi (TUAT), Tsutomu Sekibe, Shuichi Takada (ArchiTek), Hironori Nakajo (TUAT)
pp. 43 - 48
RECONF2021-66
Accelerating Deep Neural Networks on Edge Devices by Knowledge Distillation and Layer Pruning
Yuki Ichikawa, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara (Titech)
pp. 49 - 54
RECONF2021-67
Addition of DPU Training Function by Tail Layer Training
Yuki Takashima, Akira Jinguji, Hiroki Nakahara (Tokyo Tech)
pp. 55 - 60
RECONF2021-68
A study of an accelerator for CNN inference on FPGA clusters
Rintaro Sakai (Kumamoto Univ. /R-CSS), Yasuhiro Nakahara (Kumamoto Univ. /R-CCS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CCS)
pp. 61 - 66
RECONF2021-69
Ternarizing Deep Spiking Neural Network
Man Wu, Yirong Kan, Van_Tinh Nguyen, Renyuan Zhang, Yasuhiko Nakashima (NAIST)
pp. 67 - 72
RECONF2021-70
GPU acceleration of algorithm for minimal distance approximate calculation between two objects
Masumi Fukuta, Takakazu Kurokawa, Takashi Matsubara, Keisuke Iwai (NDA)
pp. 73 - 77
RECONF2021-71
An Accuracy-Aware Data Size Reduction Method of 3D Lidar SLAM
Ryuto Kojima, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 78 - 83
RECONF2021-72
FPGA Implementation of Radar Imaging for Walk-Through Security Screening System
Tatsuya Sumiya, Yuki Kobayashi, Masayuki Ariyoshi (NEC)
pp. 84 - 89
RECONF2021-73
An Implementation of a Real-time Stereo Matching System on FPGA
Kaijie Wei (Keio Univ.), Yuki Kuno (Marelli Corp.), Masatoshi Arai (Saitama Univ.), Hideharu Amano (Keio Univ.)
pp. 90 - 95
RECONF2021-74
A Light-Weight Machine Learning based Packet Routing using Online Sequential Learning
Kenji Nemoto, Masaki Furukawa, Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
pp. 96 - 101
RECONF2021-75
(See Japanese page.)
pp. 102 - 107
RECONF2021-76
A Study on Technology mapping method for Scalable Logic Module
Izumi Kiuchi, Yuya Nakazato (Kumamoto Univ.), Qian Zhao (KIT), Masahiro Iida (Kumamoto Univ.)
pp. 108 - 113
RECONF2021-77
A Preliminary Evaluation of a Compiler for RIKEN CGRA in HPC
Takuya Kojima (U.Tokyo), Carlos Cesar Cortes Torres, Boma Adhi, Yiyu Tan, Kentaro Sano (RIKEN)
pp. 114 - 119
RECONF2021-78
(See Japanese page.)
pp. 120 - 125
RECONF2021-79
Initial Design and Evaluation of RIKEN CGRA: Data-Driven Architecture for Future HPC
Boma Adhi, Carlos Cortes, Yiyu Tan (R-CCS), Takuya Kojima (Tokyo Univ.), Artur Podobas (KTH), Kentaro Sano (R-CCS)
pp. 126 - 131
RECONF2021-80
Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT)
pp. 132 - 137
RECONF2021-81
Design of a Quadruple Precision Floating-Point Arithmetic Unit for FPGAs and its Evaluation by Conjugate Gradient Method
Naoki Kakine, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ)
pp. 138 - 142
RECONF2021-82
Testing of Optimization Performance of Android DEX Compilers Based on Native Code Comparison
Naoki Yoshida, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 143 - 147
RECONF2021-83
Hard-to-Detect Hardware Trojan Attack Exploiting Coherence Control Mechanisms
Yoshiya Shikama (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 148 - 153
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.