IEICE Technical Committee Submission System
Advance Program		 Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   Prev SDM Conf / Next SDM Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Silicon Device and Materials (SDM) [schedule] [select]
Chair Tanemasa Asano (Kyushu Univ.)
Vice Chair Toshihiro Sugii (Fujitsu)
Secretary Shigeru Kawanaka (Toshiba), Hisahiro Anzai (Sony)
Assistant Syunichiro Ohmi (Tokyo Inst. of Tech.)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Nagisa Ishiura (Kwansei Gakuin Univ.)
Vice Chair Kazutoshi Wakabayashi (NEC)
Secretary Hiroyuki Ochi (Kyoto Univ.), Ichiro Kohno (Renesas)

Conference Date Tue, Oct 30, 2007 10:00 - 16:15
Wed, Oct 31, 2007 10:00 - 16:15
Topics Process, Device, Circuit Simulation, etc. 
Conference Place  
Transportation Guide http://www.jspmi.or.jp/
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Tue, Oct 30 AM 
10:00 - 11:40
(1) 10:00-10:25 Simulation on the electric conduction of semiconductor with arrayed dopant VLD2007-50 SDM2007-194 Tomohide Terunuma, Takanobu Watanabe (Waseda Univ.), Takahiro Shinada (ASMeW), Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.), Iwao Ohdomari (Waseda Univ.)
(2) 10:25-10:50 Comparative Study on Drive Current of non-Si n-Channel MOSFETs based on Quantum-Corrected Monte Calro Simulation VLD2007-51 SDM2007-195 Takashi Mori, Yuusuke Azuma, Hideaki Tsuchiya (Kobe Univ.)
(3) 10:50-11:15 Coarse-grain quantum transport simulation of ultra-small MOSFETs VLD2007-52 SDM2007-196 Gennady Mil'nikov, Nobuya Mori, Yoshinari Kamakura (Osaka Univ.), Tatsuya Ezaki (Hiroshima Univ.)
(4) 11:15-11:40 Crystalline Orientation effects on device characteristics in ultra-small multi-gate devices VLD2007-53 SDM2007-197 Hideki Minari, Daisuke Nishitani, Nobuya Mori (Osaka Univ.)
  11:40-13:00 Lunch ( 80 min. )
Tue, Oct 30 PM 
13:00 - 14:35
(5) 13:00-13:45 [Invited Talk]
Simulation technology for power devices VLD2007-54 SDM2007-198		 Ichiro Omura (Toshiba)
(6) 13:45-14:10 Electro-Thermal Compact Model for Reset Operation of Phase Change Memories VLD2007-55 SDM2007-199 Atsushi Sakai, Kenichiro Sonoda, Masahiro Moniwa, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
(7) 14:10-14:35 Study of Parasitic Resistance Behavior and Its Extraction Method on Deeply Scaled MOSFETs VLD2007-56 SDM2007-200 Hideji Tsujii, Akira Hokazono, Makoto Fujiwara, Shigeru Kawanaka, Atsushi Azuma, Nobutoshi Aoki, Yoshiaki Toyoshima (Toshiba)
  14:35-15:00 Break ( 25 min. )
Tue, Oct 30 PM 
15:00 - 16:15
(8) 15:00-15:25 Impact of Shear Strain and Quantum Confinement on <110> Channel nMOSFET with High-Stress CESL VLD2007-57 SDM2007-201 Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Eiji Tsukuda, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas Technology Corp.)
(9) 15:25-15:50 Analysis of strain-dependent hole transport characteristics in bulk Ge-pMOSFETs VLD2007-58 SDM2007-202 Hiroshi Takeda (NEC), Takeo Ikezawa, Michihito Kawada (NIS), Masami Hane (NEC)
(10) 15:50-16:15 Validation of the Effect of Full Stress Tensor in HoleTransport in Strained 65nm-node pMOSFETs VLD2007-59 SDM2007-203 Eiji Tsukuda (Renesas), Yoshinari Kamakura (Osaka Univ.), Hiroyuki Takashino, Takeshi Okagaki, Tetsuya Uchida, Takashi Hayashi, Motoaki Tanizawa, Katsumi Eikyu, Shoji Wakahara, Kiyoshi Ishikawa, Osamu Tsuchiya, Yasuo Inoue (Renesas), Kenji Taniguchi (Osaka Univ.)
Wed, Oct 31 AM 
10:00 - 11:40
(11) 10:00-10:25 An analysis of retention time of a DORGA with a constant irradiation period VLD2007-60 SDM2007-204 Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)
(12) 10:25-10:50 Fast dynamic optical reconfigurations of multi-context ORGAs VLD2007-61 SDM2007-205 Mao Nakajima, Minoru Watanabe (Shizuoka Univ.)
(13) 10:50-11:15 Fast optical configurations using context superimposition VLD2007-62 SDM2007-206 Naoki Yamaguchi, Minoru Watanabe (Shizuoka Univ.)
(14) 11:15-11:40 Study of litho weak points detecting method using TCC's eigen vector VLD2007-63 SDM2007-207 Satoshi Yoshikawa (FUJITSU VLSI), Hiroki Futatuya, Tatsuo Chijimatsu, Satoru Asai (FUJITSU)
  11:40-13:00 Lunch Break ( 80 min. )
Wed, Oct 31 PM 
13:00 - 14:40
(15) 13:00-13:50 [Invited Talk]
TBD VLD2007-64 SDM2007-208		 Masanori Hashimoto (Osaka Univ.)
(16) 13:50-14:15 Analysis of Inverter and SRAM circuits characteristics fluctuation VLD2007-65 SDM2007-209 Ryo Tanabe, Yoshio Ashizawa, Hideki Oka (Fujitsu Labs.)
(17) 14:15-14:40 The Analysis of MOSFET Characteristic Fluctuation Caused by Layout Variation VLD2007-66 SDM2007-210 Kunio Anzai, Hitoshi Tsuno, Masao Matsumura, Satoe Minami, Yohei Hiura, Akira Takeo, Fu Wingsze, Yuzo Fukuzaki, Michihiro Kanno, Naoki Nagashima, Hisahiro Ansai (Sony)
  14:40-15:00 Break ( 20 min. )
Wed, Oct 31 PM 
15:00 - 16:15
(18) 15:00-15:25 Scaled CMOS Modeling on Analog Small Signal parameters VLD2007-67 SDM2007-211 Takeshi Kida, Shin-ichi Ohkawa, Hiroo Masuda (Renesas)
(19) 15:25-15:50 Modeling of Floating-Body Effect in SOI-MOSFET with Complete Surface-Potential Description VLD2007-68 SDM2007-212 Takahiro Murakami, Makoto Ando, Norio Sadachika (Hiroshima Univ.), Takaki Yoshida (NIS), Mitiko Miura-Mattausch (Hiroshima Univ.)
(20) 15:50-16:15 Technical Trends of Mismatch Modeling on Analog CMOS Circuit VLD2007-69 SDM2007-213 Hiroo Masuda, Takeshi Kida, Shin-ichi Ohkawa (Renesas)

Contact Address and Latest Schedule Information
SDM Technical Committee on Silicon Device and Materials (SDM)   [Latest Schedule]
Contact Address Yasushiro Nishioka (Nihon University, College of Science and Technology)
TEL047-469-6482,FAX047-467-9504
E--mail:etn-u,acmsk 
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Hiroyuki OCHI (Kyoto Univ.)
E--mail:oeek-u
Tel.075-753-4803 
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/


Last modified: 2007-10-18 17:31:51


Notification: Mail addresses are partially hidden against SPAM.
[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 
[Presentation and Participation FAQ] (in Japanese)
 
[Return to VLD Schedule Page]   /   [Return to SDM Schedule Page]   /  
 
 Go Top  Go Back   Prev SDM Conf / Next SDM Conf [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan