| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2008)
Search Results: Keywords 'from:2008-04-17 to:2008-04-17'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2008-04-17 09:25 |
Tokyo | [Invited Talk]
A Single-Power-Supply 0.7V 1GHz 45nm SRAM with an Asymmetrical Unit β-ratio Memory Cell Takahiko Sasaki, Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida (Toshiba Corp.), Akihito Tohata (Toshiba Microelectronics Corp.), Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka (Toshiba Corp.)  ICD2008-1 |
A single-power supply $64kB$ SRAM is fabricated in a $45nm$ bulk CMOS technology. The SRAM operates at $1GHz$ with a $0.... [more] | ICD2008-1 pp.1-6 |
|
| ICD | 2008-04-17 10:15 |
Tokyo | [Invited Talk]
65nm Low-Power High-Density SRAM Operable at 1.0V under 3sigma Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda, Yasuhisa Shimazaki (Renesas), Kenichi Osada (Hitachi, Ltd.) ICD2008-2 |
A 1Mb SRAM is fabricated in 65nm LP process with 0.51μm2 cell. An NMOS and PMOS separately applied body bias technique a... [more] | ICD2008-2 pp.7-12 |
|
| ICD | 2008-04-17 11:15 |
Tokyo | [Invited Talk]
An 833MHz Pseudo Two-Port Embedded DRAM for Graphics Applications Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai (Toshiba), Hiroyuki Takenaka (Toshiba Microelectronics), Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka (Toshiba) ICD2008-3 |
This paper describes a pseudo two-port embedded DRAM macro developed for graphics applications. It introduces read/write... [more] | ICD2008-3 pp.13-18 |
|
| ICD | 2008-04-17 13:05 |
Tokyo | [Invited Talk]
Embedded DRAM Technology for Consumer Electronics Hiroki Shirai, Ryousuke Ishikawa, Yuichi Itoh, Takuya Kitamura, Mami Takeuchi, Takashi Sakoh, Ken Inoue, Tohru Kawasaki, Nobuyuki Katsuki, Hiroyuki Hoshizaki, Shinichi Kuwabara, Hidetaka Natsume, Masato Sakao, Takaho Tanigawa (NEC Electronics) ICD2008-4 |
This paper presents embedded DRAM device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor. Targeted for... [more] | ICD2008-4 pp.19-24 |
|
| ICD | 2008-04-17 13:55 |
Tokyo | A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology Dai Nakamura, Kazushige Kanda, Masaru Koyanagi, Toshio Yamamura, Koji Hosono, Masahiro Yoshihara (Toshiba), Toru Miwa, Yosuke Kato (Sandisk), Alex Mak, Siu Lung Chan, Frank Tsai, Raul Cernea, Binh Le (Sandisk Corp.), Eiichi Makino, Takashi Taira (Toshiba) ICD2008-5 |
A 120mm2 16Gb MLC NAND flash memory is developed using 43nm CMOS. The area is reduced by more than 9% by applying a 66 N... [more] | ICD2008-5 pp.25-30 |
|
| ICD | 2008-04-17 14:20 |
Tokyo | [Invited Talk]
NAND Flash Memory and SSD Ken Takeuchi (University of Tokyo) ICD2008-6 |
The NAND flash memory based SSD, Solid-State Drive for a PC application has been paid a lot of attention as the cost of ... [more] | ICD2008-6 pp.31-36 |
|
| ICD | 2008-04-17 15:20 |
Tokyo | [Panel Discussion]
Probing into the Potential of the Future Flash
-- An Impact of Flash Revolution -- Kazuhiko Kajigaya (Elpida), Naoharu Shinozaki (Spansion), Toshio Kakihara (HGST), Kazushige Kanda (Toshiba), Michio Kobayashi (Spansion), Makoto Saen (Hitachi), Tadahiko Sugibayashi (NEC), Ken Takeuchi (Tokyo Univ.), Hisao Tsukazawa (Toshiba) ICD2008-7 |
Flash-memory is now the driving force for the semiconductor process technology and trying to expand its new market with ... [more] | ICD2008-7 pp.37-38 |
|
| ICD | 2008-04-18 10:00 |
Tokyo | A 65nm Pure CMOS One-time Programmable Memory Using a Two-Port Antifuse Cell Implemented in a Matrix Structure Kensuke Matsufuji, Toshimasa Namekawa, Hiroaki Nakano, Hiroshi Ito, Osamu Wada, Nobuaki Otsuka (Toshiba) ICD2008-8 |
A Pure CMOS One-time Programmable（PCOP）memory using an antifuse is presented. PCOP memory adopts two-port cell architect... [more] | ICD2008-8 pp.39-44 |
|
| ICD | 2008-04-18 10:25 |
Tokyo | [Invited Talk]
* Shinji Kawai, Akira Hosogane, Shigehiro Kuge, Toshihiro Abe, Kohei Hashimoto, Tsukasa Oishi, Naoki Tsuji, Kiyohiko Sakakibara, Kenji Noguchi (Renesas) ICD2008-9 |
This paper describe an 8kB EEPROM-Emulation DataFLASH (E2FLASH) that replaces on-board EEPROM using dual-channel NOR-typ... [more] | ICD2008-9 pp.45-50 |
|
| ICD | 2008-04-18 11:15 |
Tokyo | [Invited Talk]
Current Status of Impact and Countermeasures in Environmental Neutron Induced Failures in Electric Systems
-- Evolution of Multi-Node Upset Issues -- Eishi Ibe (PERL) ICD2008-10 |
Environmental neutrons is being widely recognized as the most significant source of a variety of error modes in semicond... [more] | ICD2008-10 pp.51-56 |
|
| ICD | 2008-04-18 13:05 |
Tokyo | [Invited Talk]
15nm Planar Bulk SONOS-type Memory with Double Junstion Tunnel Layers Ryuji Ohba, Yuichiro Mitani, Naoharu Sugiyama, Shinobu Fujita (Toshiba) ICD2008-11 |
15nm gate length bulk-planar SONOS-type memory device, which has Si nanocrystal layer lying between double tunnel oxides... [more] | ICD2008-11 pp.57-62 |
|
| ICD | 2008-04-18 13:55 |
Tokyo | A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-12 |
We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) a... [more] | ICD2008-12 pp.63-68 |
|
| ICD | 2008-04-18 14:20 |
Tokyo | A 250-MHz 1-Mbit Embedded MRAM Macro Using 2T1MTJ Cell with Bitline Separation and Half-pitch Shift Architecture Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Naoki Kasai (NEC) ICD2008-13 |
A 250-MHz 1-Mbit MRAM macro is demonstrated in a 0.15-um standard CMOS process with 1.5V supply. Its clock frequency is ... [more] | ICD2008-13 pp.69-74 |
|
| ICD | 2008-04-18 14:45 |
Tokyo | Experimental proof of spin transfer switching in MRAM cell using TbCoFe/CoFeB layers with perpendicular magnetic anisotropy Masahiko Nakayama, Tadashi Kai, Naoharu Shimomura, Minoru Amano, Eiji Kitagawa, Toshihiko Nagase, Masatoshi Yoshikawa, Tatsuya Kishi, Sumio Ikegawa, Hiroaki Yoda (R&D Center, Toshiba Corp.) ICD2008-14 |
(To be available after the conference date) [more] | ICD2008-14 pp.75-78 |
|
| ICD | 2008-04-18 15:20 |
Tokyo | [Invited Talk]
Electrode Material Dependence on Binary Oxide RRAM Characteristics Yukio Tamai (Sharp), Hisashi Shima, Hiroyuki Akinaga (AIST), Yasunari Hosoi, Shigeo Ohnishi, Nobuyoshi Awaya (Sharp) ICD2008-15 |
We have synthesized Ta/Co-O/Pt RRRAM and 20ns high-speed switching and low writing current around 100$\mu$A with excelle... [more] | ICD2008-15 pp.79-82 |
|
| ICD | 2008-04-18 16:10 |
Tokyo | Realistic future trend of non-volatile semiconductor memory and feasibility study of ultra-low-cost high-speed universal non-volatile memory
-- feasibility study of BiCS type FeRAM -- Shigeyoshi Watanabe (Shonan Institute of Tech.) ICD2008-16 |
[more] | ICD2008-16 pp.83-88 |
|
[Return to Top Page]