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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2015-01-27 14:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Low power and high memory density STT-MRAM for embedded cache memory using advanced perpendicular MTJ integrations and asymmetric compensation techniques Kazutaka Ikegami, Hiroki Noguchi, Chikayoshi Kamata, Minoru Amano, Keiko Abe, Keiichi Kushida, Takao Ochiai, Naoharu Shimomura, Shogo Itai, Daisuke Saida, Chika Tanaka, Atsushi Kawasumi, Hiroyuki Hara, Junichi Ito, Shinobu Fujita (Toshiba)  SDM2014-142 |
Due to difficulty to increase clock frequency, recent processors increase cache memory to improve performance. However, ... [more] | SDM2014-142 pp.29-32 |
| ICD, CPSY | 2014-12-01 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
A transparent on-chip instruction cache for reducing power and energy consumption of NV microcontrollers Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ) ICD2014-82 CPSY2014-94 |
Demands for low energy microcontrollers which are used in sensor nodes have been increasing in recent years. Also most m... [more] | ICD2014-82 CPSY2014-94 p.43 |
| CPSY, DC (Joint) |
2014-07-30 10:45 |
Niigata | Toki Messe, Niigata | Method of Treating Read Operations' Trade-off between Throughput and Latency on Cyber-Physical Systems Hiroshi Miyake, Junpei Kamimura, Dai Kobayashi (NEC) CPSY2014-35 |
We discuss the technologies of a data store, which stores sensor data through a network, in a data center. A data stor... [more] |
CPSY2014-35 pp.149-154 |
| CPSY, DC | 2014-04-25 15:15 |
Tokyo | A Hardware Cache Mechanism for Column-Oriented Databases Akihiko Hamada, Hiroki Matsutani (Keio Univ.) CPSY2014-5 DC2014-5 |
A column-oriented store is one of structured storages (NOSQLs), in which a variable number of columns can be stored for... [more] |
CPSY2014-5 DC2014-5 pp.21-26 |
|
| NS, IN (Joint) |
2014-03-06 09:50 |
Miyazaki | Miyazaki Seagia | Cache Control Method Dispersing Content in CCN Noriaki Kamiyama (Osaka Univ./NTT), Masayuki Murata (Osaka Univ.) NS2013-210 |
As a new network architecture efficiently delivering content, CCN has been widely investigated recently. In CCN, cache m... [more] | NS2013-210 pp.197-202 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
STT-MRAM Architecture for Improving Throughput Haruki Mori, Koji Yanagida, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Koji Tsunoda, Toshihiro Sugii (LEAP) ICD2013-110 |
STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory) attracts an attention as the substitute memory of SRAM. Th... [more] | ICD2013-110 p.27 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
An Autonomous Control Cache Memory for Dynamic Variation Tolerance with Bit-Enhancing Memory Yuta Kimi, Yohei Nakata, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa (Kobe Univ.), Makoto Nagata (Kobe Univ./JST CREST), Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai (Renesas Electronics Corporation), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST CREST) ICD2013-125 |
Processor reliability is getting more critical issue since technology scaling degrades processor tolerance against power... [more] | ICD2013-125 p.59 |
| CQ, MoNA, IPSJ-DPS, IPSJ-CN, IPSJ-EIP (Joint) [detail] |
2013-09-12 14:25 |
Ishikawa | Kanazawa Institute of Technology | Traffic-based Flow Cache Port Separate Mechanism for Network Processor Hayato Yamaki, Hiroaki Nishi (Keio Univ.) CQ2013-36 |
A mechanism called Flow cache, which classifies packets into flows and caches the results of header rewrite that is equa... [more] | CQ2013-36 pp.47-52 |
| SIP, CAS, MSS, VLD | 2013-07-12 09:00 |
Kumamoto | Kumamoto Univ. | Evaluation of energy consumption for two-level cache using Non-Volatile Memory for IL1 and UL2 caches Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa (Waseda Univ.), Tadahiko Sugibayashi (NEC) CAS2013-17 VLD2013-27 SIP2013-47 MSS2013-17 |
A non-volatile memory has advantages such as low leak energy and non-volatility compared with SRAM or DRAM has high leak... [more] | CAS2013-17 VLD2013-27 SIP2013-47 MSS2013-17 pp.89-94 |
| VLD, IPSJ-SLDM | 2013-05-16 16:25 |
Fukuoka | Kitakyushu International Conference Center | SoC System Design Methodology with Fully-Coherent Cache Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10 |
As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] | VLD2013-10 pp.73-78 |
| NS, IN (Joint) |
2013-03-08 14:00 |
Okinawa | Okinawa Zanpamisaki Royal Hotel | Cooperative cache sharing among ISPs for reducing inter-ISP transit cost in content-centric networking Kazuhito Matsuda, Go Hasegawa, Masayuki Murata (Osaka Univ.) NS2012-236 |
Content-Centric Networking (CCN) has an in-network caching mechanism, which can suppress traffic volume along the route ... [more] | NS2012-236 pp.415-420 |
| VLD | 2013-03-05 15:35 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) VLD2012-151 |
This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of... [more] |
VLD2012-151 p.89 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-26 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Proposal of Speculative Memory Access Mechanism Based on Snoop Cache Yuji Sekiguchi, Hiroyoshi Jutori, Kanemitsu Ootsu, Takeshi Ohkawa, Takashi Yokota, Takanobu Baba (Utsunomiya Univ.) CPSY2012-47 |
Ratio of execution path is mostly dominated by up to two execution paths in program loops. We have developed the specula... [more] | CPSY2012-47 pp.1-6 |
| CPSY | 2012-10-12 16:20 |
Hiroshima | Cache Memory Suitability for the Graph Analysis Workloads Noboru Tanabe (Toshiba), Sonoko Tomimori, Masami Takata, Kazuki Joe (Nara Women Univ.) CPSY2012-42 |
Graph500 is a benchmark suite for big data analysis which receives attention in these years. The spatial locality of spa... [more] | CPSY2012-42 pp.67-72 |
|
| ICD, SDM | 2012-08-02 09:10 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | A Variation-Aware Low-Voltage Set-Associative Cache with Mixed-Associativity Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) SDM2012-63 ICD2012-31 |
In this paper, we propose the mixed associativity scheme using 7T/14T SRAM, which can reduce the minimum operating volta... [more] | SDM2012-63 ICD2012-31 pp.1-6 |
| KBSE, SS | 2012-07-28 14:20 |
Hokkaido | Future University Hakodate | Global Load Instruction Aggregation Considering Dimensions of Arrays Yasunobu Sumikawa, Munehiro Takimoto (TUS) SS2012-29 KBSE2012-31 |
Most of modern processors have some much faster cache memories than a main memory, and therefore, it is important to hit... [more] | SS2012-29 KBSE2012-31 pp.115-119 |
| MoNA, IE, ITE-CE, ITE-ME, IPSJ-AVM (Joint) [detail] |
2012-07-19 15:15 |
Ibaraki | University Hall, University of Tsukuba | Similar Video Retrieval Method based on the Coarsened SURF Noboru Murabayashi, Kenichi Yoshida (Univ. of Tsukuba) MoMuC2012-14 IE2012-39 |
Supposing video frame size is $720 \times 480$ and video retrieval are conducted using local features, there are thousan... [more] | MoMuC2012-14 IE2012-39 pp.19-24 |
| ICD, IPSJ-ARC | 2012-01-20 10:30 |
Tokyo | Associativity-Variable Cache to Adaptively Expand Operating Voltage Margin Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (JST) ICD2011-139 |
This paper presents a dependable cache memory for which associativity can be reconfigured dynamically. The proposed asso... [more] | ICD2011-139 pp.55-60 |
|
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-25 15:05 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Simultaneous Optimization of Cache Way Selection and Code Placement for Reducing the Memory Access Energy Consumption Junshi Takata (Kyushu Univ.), Tohru Ishihara (Kyoto Univ.), Koji Inoue (Kyushu Univ.) SIP2011-76 ICD2011-79 IE2011-75 |
The paper proposes a technique which simultaneously finds the optimal cache way allocation and code placement for given ... [more] | SIP2011-76 ICD2011-79 IE2011-75 pp.89-94 |
| VLD | 2011-03-02 14:00 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | Exact, Fast and Flexible Two-level Cache Simulation for Embedded Systems Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) VLD2010-118 |
In hierarchical cache configurations, L1 cache uses LRU as cache replacement policy but L2 and/or L3 caches use FIFO du... [more] |
VLD2010-118 pp.13-18 |
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