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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM, ICD | 2013-08-01 13:45 |
Ishikawa | Kanazawa University | [Invited Talk]
Design and diagnosis of 100GB/s Wide I/O with 4096b TSVs through Active Silicon Interposer Makoto Nagata, Satoshi Takaya (Kobe Univ.), Hiroaki Ikeda (ASET)  SDM2013-71 ICD2013-53 |
A 4096-bit wide I/O bus structure is designed and demonstrated with a three dimensional chip stack incorporating memory,... [more] | SDM2013-71 ICD2013-53 pp.31-34 |
| NLP | 2013-05-28 09:00 |
Fukuoka | Event hall, Central Library, Fukuoka University | Performance Evaluation of Markov Codes with Negative Autocorrelation and Gaussian Chip Waveforms in FD/S3 Tomoaki Yorozuya (Tokyo Denki Univ.), Mikio Hasegawa (Tokyo Univ. of Science), Yoshihiko Horio (Tokyo Denki Univ.), Kazuyuki Aihara (Univ. of Tokyo) NLP2013-18 |
A frequency division/spread spectrum system (FD/S3) has been recently proposed. A robust frequency synchronization again... [more] | NLP2013-18 pp.47-52 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | A Routing Strategy for 3-D NoCs Incorporating Bus and Network Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2012-50 |
Inductive coupled 3-D chip stacking technique allows to change types and numbers of stacked chips after fabrication. A... [more] |
CPSY2012-50 pp.15-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 17:00 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | [Keynote Address]
Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 |
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] | VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49 p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Performance evaluation of a TCP/IP Hardware Stack Directly Connectable to WEB Application Circuit Kotoko Fujita, Hakaru Tamukoh, Masatoshi Sekine (TUAT) VLD2012-95 DC2012-61 |
We have proposed a TCP/IP circuit and implemented it using a CardBus FPGA board. This paper proposes a TCP/IP hardware s... [more] | VLD2012-95 DC2012-61 pp.207-212 |
| ICD, SDM | 2012-08-02 14:15 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido | 3D Interconnect Technology by the Ultrawide-Interchip-Bus System for 3D Stacked LSI Systems Fumito Imura, Shunsuke Nemoto, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa (AIST), Michiya Hagimoto, Hiroyuki Uchida, Takashi Omori, Yasumori Hibi, Yukoh Matsumoto (TOPS Systems), Masahiro Aoyagi (AIST) SDM2012-71 ICD2012-39 |
We have proposed the ultrawide-interchip-bus system for the interchip communication of the 3-dimentional stacked LSI sys... [more] | SDM2012-71 ICD2012-39 pp.43-48 |
| NS | 2012-01-27 14:50 |
Okinawa | Ryukyu University | A study of calculation method for throughput of Input-Queued Switch with HoL Shinji Furuya, Ryuichi Kitaichi, Tetsuya Yokotani (Mitsubishi Electric Corp.) NS2011-172 |
Input-Queued Switch has been studied and implemented because its switch core circuit only has to work at the same speed ... [more] | NS2011-172 pp.157-162 |
| CS, SIP, CAS | 2011-03-03 10:50 |
Okinawa | Ohhamanobumoto memorial hall (Ishigaki)( | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98 |
As multi-processor based computers and electronic devices become the norm, a further emphasis is made on achieving task... [more] |
CAS2010-128 SIP2010-144 CS2010-98 pp.155-160 |
| SDM | 2011-02-07 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Highly Manufacturable ELK Integration Technology with Metal Hard Mask Process for High Performance 32nm-node Interconnect and Beyond S. Matsumoto, T. Harada, Y. Morinaga, D. Inagaki, J. Shibata, K. Tashiro, T. Kabe, Akihisa Iwasaki, S. Hirao, M. Tsutsue, K. Nomura, K. Seo, T. Hinomura, Naoki Torazawa, S. Suzuki (Panasonic) SDM2010-226 |
High performance 32nm-node interconnect with ELK (Extremely Low-k, k=2.4) has been demonstrated. The two main key techno... [more] | SDM2010-226 pp.59-63 |
| VLD | 2010-09-28 14:35 |
Kyoto | Kyoto Institute of Technology | A study of temperature characteristics of ring-oscillator based threshold voltage estimation Takumi Uezono, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.) VLD2010-53 |
Yield and reliability improvement is one of the most serious concerns for nanometer-technology chip designs. Recenly, s... [more] | VLD2010-53 pp.67-70 |
| RECONF | 2010-09-16 11:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Real-time detection of line segments on FPGA Jianyun Zhu, Tsutomu Maruyama (Univ. of Tsukuba) RECONF2010-19 |
In this paper, we propose an approach for detecting line segments in real-time by merging fi xed-size short line segment... [more] | RECONF2010-19 pp.7-12 |
| ICD | 2010-04-23 15:40 |
Kanagawa | Shonan Institute of Tech. | A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19 |
128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] | ICD2010-19 pp.99-102 |
| VLD | 2010-03-12 14:35 |
Okinawa | Design and Implementation of an AMBA AHB Compliant Bus Architecture on FPGA Xuan-Tu Tran, Hai-Phong Phan, Van-Huan Tran, Quang-Vinh Tran, Ngoc-Binh Nguyen (Vietnam National Univ.) VLD2009-127 |
To meet the increasing demands of recent applications, systems-on-chips (SoCs) are more and more complex and one system ... [more] | VLD2009-127 pp.169-174 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 10:40 |
Kochi | Kochi City Culture-Plaza | Implementation of Asynchronous Bus for GALS System Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) CPM2009-135 ICD2009-64 |
Although asynchronous circuit can solve problems of power consumption, speed, noise, and clockskew, the transmission is ... [more] | CPM2009-135 ICD2009-64 pp.7-12 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-04 10:40 |
Kochi | Kochi City Culture-Plaza | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Hiroshi Kasahara, Narito Fuyutsume (Tokyo Denki Univ.) CPSY2009-48 |
In a ULSI such as SoC, various IP cores developed by different firms are integrated into single-chip. Therefore problems... [more] | CPSY2009-48 pp.31-36 |
| CPSY, DC (Joint) |
2009-08-04 - 2009-08-05 |
Miyagi | A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.), Tomohiro Yoneda (NII) DC2009-18 |
This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling und... [more] | DC2009-18 pp.1-6 |
|
| AP, SAT (Joint) |
2009-07-09 15:20 |
Hokkaido | Otaru city, Hokkaido | [Invited Talk]
Space-Time-Frequency Coding for Futuristis Wireless Communications Hsiao-Hwa Chen (National Cheng Kung Univ.) AP2009-67 SAT2009-10 |
Space-time-frequency coding is a viable technology which can provide bandwidth efficient multi-dimensional signaling as ... [more] | AP2009-67 SAT2009-10 pp.131-140(AP), pp.13-22(SAT) |
| VLD | 2009-03-12 13:50 |
Okinawa | A hardmacro placement approach to reduce communication energy for deterministic-routing-based NoC Hiroshi Uchikoshi (Toyohashi Univ. of Tech.), Makoto Sugihara (Toyohashi Univ. of Tech./JST-CREST) VLD2008-147 |
An on-chip bus architecture is utilized as a communication architecture of a System-on-a-Chip. It is difficult to incre... [more] |
VLD2008-147 pp.123-128 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 10:55 |
Kanagawa | A Proposal of Message Driven IP Core Interface Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) VLD2008-96 CPSY2008-58 RECONF2008-60 |
In a ULSI such as SoC, various IP cores with different development firms are integrated in single-chip. Therefore proble... [more] | VLD2008-96 CPSY2008-58 RECONF2008-60 pp.31-36 |
|
| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-30 12:20 |
Kanagawa | A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79 |
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm effici... [more] | VLD2008-115 CPSY2008-77 RECONF2008-79 pp.141-146 |
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