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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 21 - 31 of 31 [Previous]  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD 2010-03-12
13:55		 Okinawa   An Acceleration of Soft Error Torelance Estimation Method for Sequential Circuits by Reducing the Number of States
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-126		 Soft error tolerance estimation method is necessary for the soft error aware logic design. We proposed an estimation met... [more] VLD2009-126
pp.163-168
ED, SDM 2010-02-23
10:35		 Okinawa Okinawaken-Seinen-Kaikan Fabrication of nanowire-based sequential circuits using gate-controlled GaAs three-branch nanowire junctions
Hiromu Shibata, Daisuke Nakata, Yuta Shiratori (Hokkaido Univ), Seiya Kasai (Hokkaido Univ/JST) ED2009-207 SDM2009-204		 A novel sequential circuit integrating gate-controlled three-branch nanowire junctions (TBJs) is described. A TBJ shows ... [more] ED2009-207 SDM2009-204
pp.65-70
DC 2010-02-15
11:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A binding method for testability based on resources sequential depth reduction
Takaaki Cho, Toshinori Hosokawa (Nihon Univ.) DC2009-70		 Behavioral descriptions are recently used for circuit designs on application specific fields. Behavioral synthesis is us... [more] DC2009-70
pp.31-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2009-12-03
10:00		 Kochi Kochi City Culture-Plaza An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits
Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2009-49 DC2009-36		 Soft error tolerance evaluation method is necessary for the soft error aware logic design. An evaluation method with Mar... [more] VLD2009-49 DC2009-36
pp.55-60
DC, CPSY 2009-04-21
11:00		 Tokyo Akihabara Satellite Campus, Tokyo Metropolitan Univ. Highly Reliable Sequential Circuits Considering Multiple Simultaneous Transient Faults
Hideo Kohinata, Kohei Marumoto, Masayuki Arai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) CPSY2009-1 DC2009-1		 This paper proposes a novel technique to improve the reliability of sequential circuits. The proposed technique adopts t... [more] CPSY2009-1 DC2009-1
pp.1-6
DC 2009-02-16
10:25		 Tokyo   A test pattern generation method to reduce the number of detected untestable faults on scan testing
Masayoshi Yoshimura (Kyusyu Univ.), Hiroshi Ogawa (Nihon Univ.), Yusyo Omori (Fujitsu Microelectronics), Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meizi Univ.) DC2008-69		 Scan testing is one of the most popular test method fo VLSIs. In this test, only information of the circuit structure is... [more] DC2008-69
pp.7-12
DC 2008-02-08
10:25		 Tokyo Kikai-Shinko-Kaikan Bldg. Test Generation Method for Full Scan Circuit Using Multi Cycle Capture Test
Yusho Omori, Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.), Koji Yamazaki (Meiji Univ.) DC2007-70		 Currently, scan testing is one of the most popular test methods for VLSIs. In this testing, only information of the circ... [more] DC2007-70
pp.19-24
ICD, IPSJ-ARC 2007-06-01
11:00		 Kanagawa   Design Techniques of Wave Pipelines
Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2007-28		 In order to improve rather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning... [more] ICD2007-28
pp.67-72
ICD, CPM 2005-09-08
11:20		 Tokyo Kikai-Shinko-Kaikan Bldg. Diagnostic Test Compaction for Combinational and Sequential Circuits
Yoshinobu Higami (Ehime Univ.), Kewal K Saluja (Univ. of Wisconsin), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) 		Recently, it is getting important to reduce the cost of test and fault diagnosis.
Since the cost of test and fault diag... [more]		 CPM2005-89 ICD2005-99
pp.25-30
ICD, CPM 2005-01-28
14:00		 Tokyo Kikai-Shinko-Kaikan Bldg. On Finding Don't Cares in Test Sequences for Sequential Circuits and Applications to Test Compaction and Power Reduction
Yoshinobu Higami (Ehime Univ.), Seiji Kajihara (Kyushu Inst. Tech.), Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ.) 		This paper presents a method for finding don't cares in test sequences hile keeping the original stuck-at fault coverage... [more] CPM2004-169 ICD2004-214
pp.41-46
ICD, CPM 2005-01-28
16:45		 Tokyo Kikai-Shinko-Kaikan Bldg. Development of Multiple Fault Diagnosis Based on Path-Tracing for Logic LSIs
Yukihisa Funatsu, Hiroshi Sumitomo, Kazuki Shigeta, Toshio Ishiyama (NECEL) 		For recent highly integrated and shrunk LSIs, CAD-based fault diagnosis technology which supports physical failure analy... [more] CPM2004-174 ICD2004-219
pp.71-76
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