| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-03-02 11:40 |
Okinawa | (Primary: On-site, Secondary: Online) |
eFPGA-based IP Protection of Embedded Processor Design Tomosuke Ichioka, Tanvir Ahmed, Yuko Hara (Tokyo Tech)  VLD2023-139 HWS2023-99 ICD2023-128 |
As manufacturing costs continue to grow, IC manufacturers are increasingly outsourcing IC manufacturing to third-party f... [more] | VLD2023-139 HWS2023-99 ICD2023-128 pp.209-214 |
| HWS, VLD | 2023-03-03 15:45 |
Okinawa | (Primary: On-site, Secondary: Online) |
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2022-111 HWS2022-82 |
We studied the implementation method of PUF for generating a unique ID on FPGA. We adopted a method of controlling the p... [more] | VLD2022-111 HWS2022-82 pp.209-214 |
| HWS, VLD | 2023-03-04 10:00 |
Okinawa | (Primary: On-site, Secondary: Online) |
Importance of Inverters Placement in Ring-Oscilator for Laser Irradiation Detection Shungo Hayashi (YNU), Junichi Sakamoto (AIST/YNU), Masaki Chikano, Tsutomu Matsumoto (YNU) VLD2022-115 HWS2022-86 |
Laser fault injection is known as the most efficient fault injection technique due to its high spatial controllability a... [more] | VLD2022-115 HWS2022-86 pp.233-238 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 11:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Initial Evaluation of FPGA Logic Element Placement Method Using Feature Extraction with Autoencoder Junpei Sanuki, Ibuki Watanabe, Atsushi Kubota, Tetsuo Hironaka (HCU) VLD2022-58 RECONF2022-81 |
The SA method is widely used as a logic device placement method for FPGAs. We have introduced neural networks to the pla... [more] | VLD2022-58 RECONF2022-81 pp.13-18 |
| DC | 2020-02-26 15:45 |
Tokyo | Frequency Variation of Ring Oscillators During Long-Time Operation on FPGA Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-95 |
FPGAs (Field Programmable Gate Arrays) are integrated circuits that can be implemented arbitrary logic functions by reco... [more] | DC2019-95 pp.55-60 |
|
| RECONF | 2019-09-19 14:00 |
Fukuoka | KITAKYUSHU Convention Center | A CNN-based Net Wire Length Prediction Method for FPGA Placement Cost Function Yuki Katsuda, Ryota Watanabe, Qian Zhao, Takaichi Yoshida (Kyutech) RECONF2019-21 |
The placement of an FPGA design is performed using the simulated annealing algorithm with a cost function predicting wir... [more] | RECONF2019-21 pp.3-8 |
| HWS, VLD | 2019-03-01 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs Tatsuki Otake, Hiroshi Saito (UoA) VLD2018-123 HWS2018-86 |
In this work, we study placement constraints for asynchronous circuits with bundled-data implemen-tation aimed for Field... [more] | VLD2018-123 HWS2018-86 pp.181-186 |
| VLD, HWS (Joint) |
2018-02-28 16:30 |
Okinawa | Okinawa Seinen Kaikan | Reconfiguration for Fault Tolerant FPGA Considering Incremental Multiple Faults Cheng Ma, Mineo Kaneko (JAIST) VLD2017-101 |
The report treats the reconfiguration-based fault-tolerance for FPGA applications, and proposes a method of finding a ch... [more] | VLD2017-101 pp.73-78 |
| SIP, CAS, MSS, VLD | 2017-06-19 11:00 |
Niigata | Niigata University, Ikarashi Campus | Selectable Grained Reconfigurable Architecture (SGRA) and Its Design Automation Ryosuke Koike, Takashi Imagawa (Ritsumeikan Univ.), Roberto Yusi Omaki (Synthesis), Hiroyuki Ochi (Ritsumeikan Univ.) CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5 |
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Bloc... [more] | CAS2017-5 VLD2017-8 SIP2017-29 MSS2017-5 pp.25-30 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 17:45 |
Kanagawa | Hiyoshi Campus, Keio University | A study on module allocation in multi-FPGA systems Yusuke Hirai, Kazuaki Nakazato (Univ. of the Ryukyus), Mohamed Sofian bin Abu Talip, Mishra Dipikarani, Hideharu Amano (Keio Univ.), Naoyuki Fujita (JAXA), Yasunori Osana (Univ. of the Ryukyus) VLD2013-118 CPSY2013-89 RECONF2013-72 |
Computational fluid dynamics (CFD), a powerful tool for aircraft design and other mechanical designs is a major applica... [more] |
VLD2013-118 CPSY2013-89 RECONF2013-72 pp.97-102 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:00 |
Kagoshima | ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) RECONF2013-49 |
In this paper, we propose an ILP-based method for simultaneous optimal technology mapping, placement and routing for pro... [more] | RECONF2013-49 pp.57-62 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:35 |
Kagoshima | Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN) RECONF2013-55 |
In this paper, we evaluate some logic and interconnection structures for MPLD, which is a basic architecture for reconf... [more] |
RECONF2013-55 pp.87-92 |
|
| SIP, CAS, MSS, VLD | 2013-07-11 18:00 |
Kumamoto | Kumamoto Univ. | SOM Based FPGA Placement Method Considering Wire Segment Length Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Al... [more] |
CAS2013-16 VLD2013-26 SIP2013-46 MSS2013-16 pp.83-88 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-27 09:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An ILP Formulation of Placement and Routing for PLDs Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) VLD2012-75 DC2012-41 |
In this paper, we formulate the simultaneous technology mapping, placement and routing problem for programmable gate a... [more] |
VLD2012-75 DC2012-41 pp.93-98 |
| RECONF | 2012-09-19 13:15 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | A Design Framework for Reconfigurable IPs with VLSI CADs Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-41 |
The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps... [more] | RECONF2012-41 pp.101-106 |
| RECONF | 2012-05-29 16:00 |
Okinawa | Tiruru (Naha Okinawa, Japan) | An Efficient Fault Detection and Avoidance Technique for FPGA Interconnects Yuuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-13 |
FPGA's fault detection needs a great deal of test time as compared with ASIC because FPGAs have complex structures and p... [more] | RECONF2012-13 pp.71-76 |
| RECONF | 2012-05-30 10:35 |
Okinawa | Tiruru (Naha Okinawa, Japan) | SOM-based FPGA Placement Method using Shimbel Index Tetsuro Hamada, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-20 |
A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Al... [more] |
RECONF2012-20 pp.113-118 |
| VLD | 2011-09-27 09:45 |
Fukushima | University of Aizu | Evaluation of Net-based Move in Placement for a Memory-based Reconfigurable Device MPLD Masato Inagi, Masatoshi Nakamura, Tetsuo Hironaka (Hiroshima City Univ.), Takashi Ishiguro (Taiyo Yuden) VLD2011-47 |
FPGAs realize a target circuit by realizing logic cells by LUTs and connecting wires among the logic cells by switch blo... [more] | VLD2011-47 pp.37-42 |
| RECONF | 2011-09-26 13:55 |
Aichi | Nagoya Univ. | FPGA placement based on Self-Organized Map Yasuaki Tomonari, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-26 |
Cell placement is an important phase of current FPGA(Field Programmable Gate Array) circuit design.However, this placeme... [more] | RECONF2011-26 pp.25-30 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-26 13:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | An FPGA Implementation of Array Processor Performing 3D-DCT Effectively Yuki Ikegaki, Hiroyuki Igarashi, Toshiaki Miyazaki, Stanislav G. Sedukhin (Univ. of Aizu) VLD2009-76 CPSY2009-58 RECONF2009-61 |
Ordinary array processors randomly access to input-/coefficient-data in external memories many times during the 3D-DCT, ... [more] | VLD2009-76 CPSY2009-58 RECONF2009-61 pp.41-46 |
[Return to Top Page]