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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2016-04-14 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Tosinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.)  ICD2016-10 |
A device-variation-tolerant spin-transfer-torque magnetic random access memory (STT-MRAM) cell array with a high-signal-... [more] | ICD2016-10 pp.51-56 |
| ICD | 2013-04-12 13:30 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Talk]
A Sense-Amplifier-Timing-Generating Circuit Utilizing a Statistical Method for Ultra Low Voltage SRAMs Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Sinichi Sasaki, Tomoaki Yabe (Toshiba) ICD2013-18 |
A variation tolerant sense amplifier timing generator which utilizes a statistical method is proposed. The circuit monit... [more] | ICD2013-18 pp.91-96 |
| ICD | 2013-04-12 15:55 |
Ibaraki | Advanced Industrial Science and Technology (AIST) | [Invited Lecture]
A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, Masaya Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai (Renesas Electronics) ICD2013-22 |
An 18Mb full ternary CAM with 0.3V match line sense amplifier (LV-MA) is designed and fabricated in 65nm bulk CMOS proce... [more] | ICD2013-22 pp.115-120 |
| ICD, IPSJ-ARC | 2013-02-01 11:40 |
Tokyo | Programming Circuit of Multi-level ReRAM Utilizing Voltage Sense-Amplifier Taiki Ibe, Kazuya Nakayama, Akio Kitagawa (Kanazawa Univ.) ICD2012-126 |
For multi-level ReRAM memory, a novel read circuit using a VSA (Voltage Sense Amplifier) is proposed. This circuit compa... [more] | ICD2012-126 pp.45-49 |
|
| SDM, ED (Workshop) |
2012-06-27 13:45 |
Okinawa | Okinawa Seinen-kaikan | A High Performance SRAM Sense Amplifier with Vertical MOSFET Hyoungjun Na, Tetsuo Endoh (Tohoku Univ.) |
In this paper, a high performance SRAM sense amplifier with vertical MOSFET is proposed, and its performances are invest... [more] | |
| SDM, ED (Workshop) |
2012-06-27 18:15 |
Okinawa | Okinawa Seinen-kaikan | Design of a Differential Paired eFuse One-Time Programmable Memory IP and its Measurement Huiling Yang, Min-Sung Kim, Ji-Hye Jang, Mu-hun Park, Pan-Bong Ha, Young-Hee Kim (Changwon National Univ.) |
In this paper, we design an 8-bit eFuse OTP memory IP using differential paird eFuse cells which have a small sensing re... [more] | |
| SDM, ICD | 2011-08-26 13:40 |
Toyama | Toyama kenminkaikan | Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) SDM2011-89 ICD2011-57 |
An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] | SDM2011-89 ICD2011-57 pp.93-97 |
| ICD, ITE-IST | 2011-07-21 09:55 |
Hiroshima | Hiroshima Institute of Technology | A Sense Amplifier with High Speed Pre-Charge Operation for Ultra-Low-Voltage SRAM Chotaro Masuda, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kove Univ.) ICD2011-22 |
We propose a current latch sense amplifier with a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is capable of hig... [more] |
ICD2011-22 pp.7-12 |
| ICD | 2011-04-19 09:55 |
Hyogo | Kobe University Takigawa Memorial Hall | A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe (Toshiba) ICD2011-9 |
A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static ... [more] | ICD2011-9 pp.49-54 |
| ICD | 2010-04-22 12:05 |
Kanagawa | Shonan Institute of Tech. | Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6 |
A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] | ICD2010-6 pp.29-33 |
| ICD, ITE-IST | 2007-07-26 16:05 |
Hyogo | A 356-µW, 433-MHz, Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks Hyeokjong Lee, Shinji Mikami, Takashi Takeuchi, Masumi Ichien, Hiroshi Kawaguchi, Chikara Ohta, Masahiko Yoshimoto (Kobe Univ.) ICD2007-50 |
We describe a low-power voltage amplifier that is suitable for RF (radio frequency) receivers in a WSN (wireless sensor ... [more] | ICD2007-50 pp.77-82 |
|
| ICD | 2007-04-12 11:10 |
Oita | [Invited Talk]
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current Akira Kotabe, Satoru Hanzawa (Hitachi), Naoki Kitai (Hitachi ULSI), Kenichi Osada, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura (Hitachi), Masahiro Moniwa (Renesas), Takayuki Kawahara (Hitachi) ICD2007-5 |
An experimental 512-kB embedded Phase Change Memory (PCM) is developed in a 0.13-μm 1.5-V CMOS technology. Three circuit... [more] | ICD2007-5 pp.23-28 |
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| ICD | 2006-04-13 10:45 |
Oita | Oita University | [Special Invited Talk]
Sub-1V DRAM Design Takayuki Kawahara (Hitachi Central Research Lab.) |
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,... [more] | ICD2006-4 pp.19-24 |
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