Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, ICD, VLD |
2025-03-05 14:00 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Error Correation Methods with Node Redundancy Considering Node Level in DMFB Koki Suzuki, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
[more] |
|
HWS, ICD, VLD |
2025-03-05 14:25 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Speeding Up a Routing Method Considering Droplet Division on MEDA Biochips by Dijkstra's Method Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ.), Ankur Gupta (NSUT) |
(To be available after the conference date) [more] |
|
VLD, RECONF |
2025-01-16 15:30 |
Kanagawa |
Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Hardware Design Using Python for Full Hardware Implementation of RTOS-Based Systems Hikaru Shiga, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2024-85 RECONF2024-115 |
This paper proposes a method for describing hardware design and testing using Python in the context of a technique that ... [more] |
VLD2024-85 RECONF2024-115 pp.53-58 |
RECONF, VLD |
2024-01-30 13:20 |
Kanagawa |
AIRBIC Meeting Room 1-4 (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] |
VLD2023-94 RECONF2023-97 pp.81-86 |
HWS, VLD |
2023-03-01 16:50 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs Tomohisa Kawakami, Chiharu Shiro (Ritsumeikan Univ.), Hiroki Nishikawa (Osaka Univ.), Kong Xiangbo, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeikan Univ.) VLD2022-83 HWS2022-54 |
[more] |
VLD2022-83 HWS2022-54 pp.61-66 |
IPSJ-SLDM, RECONF, VLD [detail] |
2023-01-24 11:20 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips Chiharu Shiro (Ritsumeiakn Univ.), Hiroki Nishikawa (Osaka Univ.), Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita (Ritsumeiakn Univ.) VLD2022-67 RECONF2022-90 |
Digital microfluidic biochips (DMFB) have attracted attention in the biochemical and medical industries. A micro electro... [more] |
VLD2022-67 RECONF2022-90 pp.45-49 |
VLD, HWS [detail] |
2022-03-07 10:00 |
Online |
Online (Online) |
A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Operations in High-Level Synthesis Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2021-78 HWS2021-55 |
This paper studies a scheduling algorithm for high-level synthesis that takes into account the difference in delay betwe... [more] |
VLD2021-78 HWS2021-55 pp.13-18 |
RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] |
2022-01-24 10:20 |
Online |
Online (Online) |
Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] |
VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-02 09:45 |
Online |
Online (Online) |
Routing of Delivery Drones with Load- and Wind-Dependent Flight Speed Satoshi Ito, Keishi Akaiwa, Yusuke Funabashi, Hiroki Nishikawa, Xiangbo Kong (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2021-33 ICD2021-43 DC2021-39 RECONF2021-41 |
Drone-based package delivery is expected to be a promising way to solve the last mile problem. The flight speed of drone... [more] |
VLD2021-33 ICD2021-43 DC2021-39 RECONF2021-41 pp.93-98 |
HWS, VLD [detail] |
2021-03-03 14:55 |
Online |
Online (Online) |
Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware
implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
HWS, VLD [detail] |
2021-03-03 15:20 |
Online |
Online (Online) |
Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks in Multicore Embedded Systems Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2020-76 HWS2020-51 |
(To be available after the conference date) [more] |
VLD2020-76 HWS2020-51 pp.44-49 |
HWS, VLD [detail] |
2021-03-04 09:55 |
Online |
Online (Online) |
High-level synthesis of approximate circuits with two-level accuracies Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55 |
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] |
VLD2020-80 HWS2020-55 pp.67-72 |
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] |
2020-01-23 11:25 |
Kanagawa |
Raiosha, Hiyoshi Campus, Keio University (Kanagawa) |
Full Hardware Synthesis of FreeRTOS-Based Systems Wakako Nakano, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2019-70 CPSY2019-68 RECONF2019-60 |
[more] |
VLD2019-70 CPSY2019-68 RECONF2019-60 pp.105-110 |
HWS, VLD |
2019-02-27 11:15 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
A Case Study on Approximate Multipliers for MNIST CNN Kenta Shirane, Takahiro Yamamoto (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-95 HWS2018-58 |
[more] |
VLD2018-95 HWS2018-58 pp.13-18 |
HWS, VLD |
2019-02-27 14:30 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
Function-level Module Sharing with High-level Synthesis Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-100 HWS2018-63 |
High-Level Synthesis (HLS) which automatically synthesizes a Resister-Transfer Level (RTL) circuit from a behavioral des... [more] |
VLD2018-100 HWS2018-63 pp.43-48 |
HWS, VLD |
2019-02-27 14:55 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
High-Level Synthesis of the CHStone Benchmark Programs with SDSoC Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-101 HWS2018-64 |
In recent years, High-Level Synthesis (HLS), which automatically generates hardware circuits from software program, have... [more] |
VLD2018-101 HWS2018-64 pp.49-54 |
HWS, VLD |
2019-02-27 16:45 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-105 HWS2018-68 |
FPGA-based manycore architectures attract an increasing attention in order to realize high-performance embedded systems.... [more] |
VLD2018-105 HWS2018-68 pp.73-78 |
HWS, VLD |
2019-03-01 10:00 |
Okinawa |
Okinawa Ken Seinen Kaikan (Okinawa) |
Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware
design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-05 09:55 |
Hiroshima |
Satellite Campus Hiroshima (Hiroshima) |
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-41 DC2018-27 |
[more] |
VLD2018-41 DC2018-27 pp.7-11 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima |
Satellite Campus Hiroshima (Hiroshima) |
A Case Study on Memory Architecture Exploration for FPGA-based Manycores Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-53 DC2018-39 |
In the design of high-performance embedded systems, FPGA-based manycores attract an increasing attention. In embedded sy... [more] |
VLD2018-53 DC2018-39 pp.101-106 |