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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 10:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control Kousei Kaizu, Kimiyoshi Usami (SIT)  VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 |
Non-Volatile Flip Flops (NVFF) using Magnetic Tunnel Junction (MTJ) enable non-volatile power gating and reduce leakage ... [more] | VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 pp.88-93 |
| VLD, HWS [detail] | 2022-03-07 14:30 |
Online | Online | MTJ-based non-volatile SRAM circuit with Approximate Image-data Storing for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-86 HWS2021-63 |
Non-volatile memory (NVM) using magnetic tunnel junction (MTJ) devices can prevent the increase in leakage current, whic... [more] | VLD2021-86 HWS2021-63 pp.51-56 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2021-12-01 10:10 |
Online | Online | MTJ-based non-volatile SRAM circuit with data-aware store control for energy saving Hisato Miyauchi, Kimiyoshi Usami (SIT) VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 |
In recent years, the increase of leakage power in LSIs has become a problem, and one of the methods to reduce the leakag... [more] | VLD2021-19 ICD2021-29 DC2021-25 RECONF2021-27 pp.13-18 |
| HWS, VLD [detail] | 2020-03-04 13:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
MTJ-based Nonvolatile Flip-Flop Circuit Using Dual Power Supplies for Low-voltage Operation Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2019-99 HWS2019-72 |
One of the leakage reduction techniques is nonvolatile power gating(NVPG) by using magnetic tunnel junction(MTJ). In the... [more] | VLD2019-99 HWS2019-72 pp.31-36 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| EE, WPT (Joint) |
2017-10-17 10:20 |
Miyagi | Tohoku Univ. | Basic Study of Self-convergent Beam Formation by a Both-sides Retrodirective System Takayuki Matsumuro (Ryukoku Univ.), Yohei Ishikawa (Kyoto Univ.), Masashi Yanagase (Murata Co., Ltd.), Naoki Shinohara (Kyoto Univ.) WPT2017-38 |
We propose a new wireless power transmission system applying retrodirective scheme reradiating microwave in the arrival ... [more] | WPT2017-38 pp.13-16 |
| ICD | 2017-04-21 09:35 |
Tokyo | [Invited Lecture]
Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10 |
Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) ... [more] | ICD2017-10 pp.51-56 |
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| VLD | 2017-03-01 14:00 |
Okinawa | Okinawa Seinen Kaikan | Fine-Grain Power Gating of MTJ-based Non-volatile Cache and Dynamic Selection Control for Storing Cache Lines Shota Enokido, Kimiyoshi Usami (SIT) VLD2016-102 |
Non-volatile Power Gating(NVPG) is a technique to power gate memory elements to reduce leakage power while keeping the s... [more] | VLD2016-102 pp.1-6 |
| VLD | 2017-03-01 14:25 |
Okinawa | Okinawa Seinen Kaikan | A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVF... [more] | VLD2016-103 pp.7-12 |
| VLD | 2017-03-02 09:50 |
Okinawa | Okinawa Seinen Kaikan | Reliability enhancement of Hierarchical data reading circuit of Wafer scale mask ROM Takaaki Yokoyama, Ochi Hiroyuki (Ritsumeikan Univ) VLD2016-110 |
In the national libraries of developed countries, there is a demand to store large amounts of data in a digital form ove... [more] | VLD2016-110 pp.49-54 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| VLD | 2016-03-01 16:15 |
Okinawa | Okinawa Seinen Kaikan | Noise reduction effect for input dependence of Zigzag Power Gating Tadahiro Kanamoto, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-128 |
In Power Gating techniques to reduce leakage current, there is the technology called Zigzag Power Gating. Zigzag Power G... [more] | VLD2015-128 pp.99-103 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 16:20 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-57 DC2015-53 |
This paper describes a sleep control technique using leakage monitor circuit to implement Fine-Grain Power Gating (FGPG)... [more] | VLD2015-57 DC2015-53 pp.129-134 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:40 |
Hokkaido | Hokkaido University | Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] | CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 pp.213-218 |
| ICD | 2014-04-17 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine Shoun Matsunaga (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi (NEC), Masanori Natsui, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2014-8 |
We demonstrate a 1-Mb nonvolatile TCAM-based search engine using 90-nm CMOS and perpendicular MTJ technologies for an ul... [more] | ICD2014-8 pp.39-44 |
| ICD | 2014-04-18 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop Hiroki Koike (Tohoku Univ.), Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Sadahiko Miura, Hiroaki Honjo, Tadahiko Sugibayashi (NEC), Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh (Tohoku Univ.) ICD2014-17 |
We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel jun... [more] | ICD2014-17 pp.85-90 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 13:25 |
Kagoshima | A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.) CPM2013-116 ICD2013-93 |
In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel juncti... [more] | CPM2013-116 ICD2013-93 pp.49-53 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:15 |
Kagoshima | Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers Yudai Itoi, Shinji Kimura (Waseda Univ.) VLD2013-82 DC2013-48 |
Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attenti... [more] | VLD2013-82 DC2013-48 pp.147-152 |
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