Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 14:20 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
On the performance evaluation of a PUF circuit using the Delay Testable Circuit under temperature effects Eisuke Ohama, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 |
In this study, we have proposed a method to make the design-for-testability circuity function as a security mechanism by... [more] |
VLD2022-46 ICD2022-63 DC2022-62 RECONF2022-69 pp.156-161 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 14:45 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Evaluation of testing TSVs using the delay testable circuit implemented in a 3D IC Keigo Takami (Tokushima Univ. Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 |
Testing TSVs used for chip-to-chip interconnection in 3D stacked ICs is a challenging problem. We have proposed a bounda... [more] |
VLD2022-47 ICD2022-64 DC2022-63 RECONF2022-70 pp.162-167 |
DC, SS |
2019-10-24 16:00 |
Kumamoto |
Kumamoto Univ. |
A Non-scan Online Test Based on Covering n-Time State Transition Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) SS2019-19 DC2019-47 |
As one of the means to avoid the fault due to the deteriorate over time of VLSI, online test is used to monitor the outp... [more] |
SS2019-19 DC2019-47 pp.37-42 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima |
Satellite Campus Hiroshima |
Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC.
However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
DC |
2018-02-20 10:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79 |
TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more] |
DC2017-79 pp.13-18 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-06 15:20 |
Kumamoto |
Kumamoto-Kenminkouryukan Parea |
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43 |
Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] |
VLD2017-37 DC2017-43 pp.61-66 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:25 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2016-62 DC2016-56 |
With improvement of semiconductor manufacturing process, small delay becomes more important cause of timing failures.
... [more] |
VLD2016-62 DC2016-56 pp.105-110 |
ICD |
2016-04-14 10:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Lecture]
A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics) ICD2016-1 |
An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micr... [more] |
ICD2016-1 pp.1-6 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki |
Nagasaki Kinro Fukushi Kaikan |
Easily-testable Carry Select Adder with Online Error Detection Capability Nobutaka Kito (Chukyo Univ.) VLD2015-72 DC2015-68 |
An easily testable multi-block carry select adder with online error detection capability is proposed. An easily testable... [more] |
VLD2015-72 DC2015-68 pp.225-230 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita |
B-ConPlaza |
Investigation of the area reduction of observation part and control part in TSV fault detection circuit Youhei Miyamoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2014-72 DC2014-26 |
Since delay caused by an open TSV is usually very small, it is defficult to detect. Therefore, we have proposed a TSV fa... [more] |
VLD2014-72 DC2014-26 pp.3-8 |
VLD |
2014-03-03 16:25 |
Okinawa |
Okinawa Seinen Kaikan |
Secure scan design using improved random order scans and its evaluations Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-141 |
Scan test using scan chains is one of the most important DFT techniques.
On the other hand, scan-based attacks are repo... [more] |
VLD2013-141 pp.43-48 |
DC |
2014-02-10 09:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Module Coupling Overhead Aware Scan Chain Construction Meguru Komatsu, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-79 |
It is necessary to minimize the impact on the layout of the design changes to Design for Testability
(DFT). Especially,... [more] |
DC2013-79 pp.1-5 |
DC |
2014-02-10 09:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan Hiroki Sakurai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) DC2013-80 |
In recent deep sub-micron (DSM) ICs, it is difficult to detect open and
short defects since they do not behave like co... [more] |
DC2013-80 pp.7-12 |
DC |
2014-02-10 09:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] |
DC2013-81 pp.13-18 |
DC, CPSY |
2013-04-26 16:40 |
Tokyo |
|
On-Chip Delay Measurement Using Adjacent Test Architecture Kentaroh Katoh (TNCT) CPSY2013-8 DC2013-8 |
This paper proposes an on-chip delay measurement using adjacent test architecture with TDC (Time to Digital Converter). ... [more] |
CPSY2013-8 DC2013-8 pp.43-48 |
DC |
2013-02-13 13:55 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On Fault detection method considering adjacent TSVs for a delay fault in TSV Masanori Nakamura, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ.of Tokushima) DC2012-85 |
We propose a fault detection method for a TSV (through-Silicon via) considering adjacent TSVs for detecting delay caused... [more] |
DC2012-85 pp.31-36 |
DC |
2012-02-13 14:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Test Generation Method for Synchronously Designed QDI Circuits Koki Uchida, Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST) DC2011-83 |
Quasi-Delay-Insensitive(QDI) design has been attracting attention as one of the practical techniques for implementation ... [more] |
DC2011-83 pp.43-48 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:00 |
Miyazaki |
NewWelCity Miyazaki |
Modeling Economics of LSI Design and Manufacturing for Selecting Test Design. Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2011-71 DC2011-47 |
Many test designs (or DFTs: designs-for-testability) have been proposed to overcome some issues around LSI testing.
In... [more] |
VLD2011-71 DC2011-47 pp.115-120 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:30 |
Miyazaki |
NewWelCity Miyazaki |
On the design for testability method using Time to Digital Converter for detecting delay faults Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima) VLD2011-84 DC2011-60 |
We propose the design for testability method for detecting delay fault that can form a TDC(Time-to-Digital Converter) to... [more] |
VLD2011-84 DC2011-60 pp.185-190 |
DC |
2011-06-24 14:40 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
International Conference Report - VTS2011(29th IEEE VLSI Test Symposium) Kazumi Hatayama (NAIST) DC2011-11 |
This talk provide a report of VTS2011 (29th IEEE VLSI Test Symposium), which was held in Dana Point, California, USA, in... [more] |
DC2011-11 pp.17-22 |