Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2007] | [2008] | [2009] | [2010] | [2011] | [2012] | [2013] | [Japanese] / [English]
SDM2010-124
On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks
Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.)
pp. 1 - 4
SDM2010-125
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration
Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa (Panasonic)
pp. 5 - 10
SDM2010-126
An Over 20,000 Quality Factor On-Chip Relaxation Oscillator using Voltage Averaging Feedback with a Chopped Amplifier
Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho (Panasonic Corp.)
pp. 11 - 16
SDM2010-127
A 2.7mW 4th-Order Active Gm-RC Bandpass Filter with 60MHz Center Frequency and Digital/Analog Tuning Techniques
Jingbo Shi, Takayuki Konishi, Toru Kashimura, Shoichi Masui (Tohoku Univ)
pp. 17 - 22
SDM2010-128
Investigation of Analog-to-Digital Converters using Time Dimension
Masao Takayama, Takuji Miki, Shiro Dosho (Panasonic)
pp. 23 - 28
SDM2010-129
10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects
Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho (Panasonic)
pp. 29 - 34
SDM2010-130
Pull-up/pull-down circuits with no static current consumption
Tatsuya Ueno (Yamatake Corp.)
pp. 35 - 37
SDM2010-131
1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi)
pp. 39 - 44
SDM2010-132
Design Constraint of Fine Grain Supply Voltage Control LSI
-- In the case of Power Gating Technique --
Atsuki Inoue (Fujitsu Lab. Ltd.)
pp. 45 - 49
SDM2010-133
Design Constraint of Fine Grain Supply Voltage Control LSI
-- In the case of DVFS Technique --
Atsuki Inoue (Fujitsu Lab. Ltd.)
pp. 51 - 54
SDM2010-134
Power Analysis and Power Reduction Techniques of a 128GFLOPS/58W SPARC64VIIIfx Processor for Peta-scale Computing
Yukihito Kawabe (Fujitsu Lab.), Hiroshi Okano, Ryuji Kan, Toshio Yoshida, Iwao Yamazaki, Hitoshi Sakurai, Mikio Hondou, Nobuyuki Matsui, Hideo Yamashita, Tatsumi Nakada, Takumi Maruyama, Takeo Asakawa (Fujitsu)
pp. 55 - 58
SDM2010-135
[Invited Talk]
MEMS/BEANS-Enabled Green Technology
Norihisa Miki (Keio Univ./BEANS Project)
pp. 59 - 64
SDM2010-136
[Invited Talk]
Development of MEMS Technologies for Micro Energy Systems
Yuji Suzuki (Univ. of Tokyo.)
pp. 65 - 69
SDM2010-137
[Invited Talk]
A Wide-Area Sensor Network with Fiber Optic Power Supply
Yosuke Tanaka, Takashi Kurokawa (Tokyo Univ. of A & T)
pp. 71 - 76
SDM2010-138
Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs
Shuhei Tanakamaru (Univ. of Tokyo), Atsushi Esumi, Mitsuyoshi Ito, Kai Li (SIGLEAD), Ken Takeuchi (Univ. of Tokyo)
pp. 77 - 82
SDM2010-139
A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD
Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka (Univ. of Tokyo), Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo)
pp. 83 - 88
SDM2010-140
A 60% Higher Write Speed, 4.2Gbps, 24-Channel 3D-Solid State Drive (SSD) with NAND Flash Channel Number Detector and Intelligent Program-Voltage Booster
Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku (Univ. of Tokyo), Shinji Miyamoto, Hiroto Nakai (Toshiba), Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo)
pp. 89 - 94
SDM2010-141
[Invited Talk]
Development of sub-10um Thinning Technology using Actual Device Wafers
Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo)
pp. 95 - 97
SDM2010-142
Study of stacked MRAM for universal memory
Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 99 - 104
SDM2010-143
Study of stacked FeRAM using ITO channel
Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech)
pp. 105 - 110
SDM2010-144
Direct Measurement and Analysis of Static Noise Margin in SRAM Cells Using DMA TEG
Toshiro Hiramoto, Makoto Suzuki, Takuya Saraya, Ken Shimizu (Univ. of Tokyo), Akio Nishida, Shiro Kamohara, Kiyoshi Takeuchi, Tohru Mogami (MIRAI-Selete)
pp. 111 - 114
SDM2010-145
70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection
Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo)
pp. 115 - 120
SDM2010-146
A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element
Jun Furuta (Kyoto Univ.), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.)
pp. 121 - 124
SDM2010-147
Application of spin MOSFET to Nonvolatile and Reconfigurable LSIs
Tomoaki Inokuchi, Takao Marukame, Tetsufumi Tanamoto, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito (Toshiba Corporation)
pp. 125 - 129
SDM2010-148
Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor
Takamichi Hayashi, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 131 - 136
SDM2010-149
Pattern Layout Methods of System LSI with SGT
Takahiro Kodama, Shigeyoshi Watanabe (Shonan Inst. of Tech.)
pp. 137 - 142
SDM2010-150
Random Drain Current Variation Caused by "Current-Onset Voltage" Variability in Scaled MOSFETs
Tomoko Mizutani (Univ. of Tokyo), Takaaki Tsunomura (MIRAI-Selete), Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete)
pp. 143 - 148
SDM2010-151
On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs and Multi-FinFETs
Yongxun Liu, Kazuhiko Endo, Shinich Ouchi (AIST), Takahiro Kamei (Meiji Univ.), Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa (AIST), Tetsuro Hayashida (Meiji Univ.), Kunihiro Sakamoto, Takashi Matsukawa (AIST), Atsushi Ogura (Meiji Univ.), Meishoku Masahara (AIST)
pp. 149 - 154
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.