Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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DC2011-28
The RG-DTM PUF utilizing the Time to Digital Converter
Takahiko Murayama, Mitsuru Shiozaki, Kota Furuhashi, Takeshi Fujino (Ritsumeikan Univ.)
pp. 1 - 6
DC2011-29
Scan-based Attack against Triple DES Cryptosystems Using Scan Signatures
Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 7 - 12
DC2011-30
On Secure and Testable Scan Design Utilizing Shift Register Quasi-Equivalents
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (Osaka Gakuin Univ.), Hideo Tamamoto (Akita Univ.)
pp. 13 - 18
DC2011-31
Degradation of Oscillation Frequency of Ring Oscillators Placed on a 90 nm FPGA
Shouhei Ishii, Kazutoshi Kobayashi (KIT)
pp. 19 - 24
DC2011-32
High accuracy of system LSI energy estimation
Wang Xiang (Kyushu Univ.), Norifumi Yoshimatsu (ISIT), Kazuaki Murakami (Kyushu Univ.)
pp. 25 - 30
DC2011-33
An Interrupt Service Handler in Hardware for Ultra-Low Latency Response
Naotaka Maruyama (Kernelon Silicon), Tohru Ishihara (Kyoto Univ.), Hiroaki Takada (Nagoya Univ.), Hiroto Yasuura (Kyushu Univ.)
pp. 31 - 36
DC2011-34
Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links
Atsushi Matsumoto (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Takahiro Hanyu (Tohoku Univ.)
pp. 37 - 42
DC2011-35
Performance Evaluation of Soft-Error Tolerant Multiple Modular Processors Implemented with Redundant and Non-Redundant Flip-Flops
Shogo Okada, Masaki Masuda (KIT), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (KIT)
pp. 43 - 48
DC2011-36
A Dynamically Configurable NoC Test Access Mechanism
Takieddine Sbiai, Kazuteru Namba, Hideo Ito (Chiba Univ.)
pp. 49 - 54
DC2011-37
A Consideration on Wire-Sizing of Input Signals for System on Glass Liquid Crystal Display
Taichi Suizu, Shuji Tsukiyama (Chuo Univ.)
pp. 55 - 60
DC2011-38
Analytical Placement for Convex Blocks
Tomoaki Gotanda, Masatomo Kuwano, Yasuhiro Takashima (Univ. of Kitakyushu)
pp. 61 - 65
DC2011-39
An Acceleration Method for Power Grid Analysis using Block-Iterative Algorithm
Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)
pp. 67 - 71
DC2011-40
A Fast Transient Analysis of Linear Circuit using Quasi Zero Variance Importance Sampling
Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)
pp. 73 - 78
DC2011-41
CMOS Op-amp Offset Calibration Technique Using a Closed Loop Offset Amplifier and Compact Resistor String DAC
Hiroyuki Morimoto, Hiroaki Goto (KIT), Hajime Fujiwara (NJR), Kazuyuki Nakamura (KIT)
pp. 79 - 84
DC2011-42
A study on parameter estimation for modeling of random-telegraph noise
Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato (Kyoto Univ.)
pp. 85 - 90
DC2011-43
Synthesis of efficient data fetch mechanism from the high level communication description
Masato Minato, Yuki Ando, Seiya Shibata (Nagoya Univ.), Tomoo Kinoshita (Soliton Systems), Shinya Honda, Hiroaki Takada (Nagoya Univ.)
pp. 91 - 96
DC2011-44
A Runtime Mechanism for Managing of the Scratch-Pad Memory within Real-Time Operating Systems
Hideki Takase, Hiroaki Takada (Nagoya Univ.)
pp. 97 - 102
DC2011-45
Automatic Loop Fusion for High Level Synthesis using Outer Loop Shifting
Yuta Kato, Kenshu Seto, Takuya Maruizumi (TCU)
pp. 103 - 108
DC2011-46
A Hardware/Software Co-Design Method Optimized for High-Level Synthesis
-- Application to Android Platforms --
Hitoki Ito, Kiyofumi Tanaka (JAIST)
pp. 109 - 113
DC2011-47
Modeling Economics of LSI Design and Manufacturing for Selecting Test Design.
Noboru Shimizu, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 115 - 120
DC2011-48
Improvement of Test Data Compression Rate for Chiba-Scan Testing by Reconstructing Scan Chain
Masato Akagawa, Kazuteru Namba, Hideo Ito (Chiba univ.)
pp. 121 - 126
DC2011-49
A Scan Chain Construction Method to Reduce Test Data Volume on BAST
Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
pp. 127 - 132
DC2011-50
A BIST-Aided Scan Test using Shifting Inverter Code and a TPG Method for Test Data Reduction
Yasuhiko Okada, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
pp. 133 - 138
DC2011-51
[Fellow Memorial Lecture]
Safe, Secure and Reliable Society by Electronics and InformationTechnology
-- What and how should we protect? --
Shuichi Sakai (UT)
pp. 139 - 140
DC2011-52
Layout Methodology for Self-Alinged Double Patterning
Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto (Toshiba)
pp. 141 - 146
DC2011-53
An Integer Linear Programming based Multiple Task Allocation Method for Fault Tolerance in Network on Chip
Hiroshi Saito (Univ. Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC)
pp. 147 - 152
DC2011-54
Ymtools: an infrastructure for research and development of logic synthesis and verification
Yusuke Matsunaga (Kyushu Univ.)
pp. 153 - 158
DC2011-55
A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning
Mineo Kaneko (JAIST)
pp. 159 - 164
DC2011-56
A Hardware Development by C Source Code Visualization
Akitoshi Matsuda, Shinichi Baba, Hirofumi Takamoto (Q's Forum)
pp. 165 - 170
DC2011-57
[Keynote Address]
Lithography : past, present, and future
Shigeki Nojima (Toshiba)
p. 171
DC2011-58
[Invited Talk]
Ultra Low Voltage Subthreshold Circuit Design
Masanori Hashimoto (Osaka Univ.)
pp. 173 - 178
DC2011-59
Capture power reduction in multi-cycle test structure
Hisato Yamaguchi, Makoto Matsuzono, Kohei Miyase, Yasuo Sato, Seiji Kajihara (KIT)
pp. 179 - 183
DC2011-60
On the design for testability method using Time to Digital Converter for detecting delay faults
Hiroyuki Makimoto, Hiroyuki Yotsuyanagi, Masaki Hashizume (Univ. of Tokushima)
pp. 185 - 190
DC2011-61
A study on path selection results of an adaptive field test with process variation and aging degradation for VLSI
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyu Univ)
pp. 191 - 195
DC2011-62
A Method of Thermal Uniformity Control During BIST
Eri Murata (NAIST), Satoshi Ohtake (Oita Univ.), Yasuhiko Nakashima (NAIST)
pp. 197 - 202
DC2011-63
A length difference reduction algorithm by using flow in set pair routing problem for single layer PCB routing
Yusaku Yamamoto, Atsushi Takahashi (Osaka Univ.)
pp. 203 - 208
DC2011-64
An Improved Simulated Annealing for 3D Packing with Sequence Triple and Quintuple Representations
Yiqiang Sheng (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.), Shuichi Ueno (Tokyo Inst. of Tech.)
pp. 209 - 214
DC2011-65
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application
Takao Kawano (Tohoku Univ.), Naoya Onizawa (McGill Univ.), Atsushi Matsumoto, Takahiro Hanyu (Tohoku Univ.)
pp. 215 - 220
DC2011-66
Power-Gating Circuit Scheme for Transient-Glitch Energy Reduction
Yuya Ohta, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 221 - 226
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.