Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2012-107
Architecture Evaluation of a Reconfigurable Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN)
pp. 1 - 6
VLD2012-108
A Design Method of Network-on-Chip Architecture for FPGA
Hideki Katabami, Hiroshi Saito (Aizu Univ.)
pp. 7 - 12
VLD2012-109
A Study of 3D FPGA Architecture Using Face-to-Face Stacked Routing Layer
Yusuke Iwai, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 13 - 18
VLD2012-110
Performance Evaluation of Parametalized Data Compression Hardware for Floating-Point Data Stream
Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 19 - 24
VLD2012-111
An Architecture for IPv6 Lookup Using Parallel Index Generation Units
Hiroki Nakahara (Kaoghima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT)
pp. 25 - 30
VLD2012-112
Implementation of a neural network for FPGA-based digital DC-DC converters
Yoshihiko Yamabe, Masashi Motomura, Kentaro Yamashita, Hidenori Maruta, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.)
pp. 31 - 36
VLD2012-113
[Invited Talk]
Challenges and Opportunities for Normally-Off Computing
Hiroshi Nakamura (U. Tokyo)
p. 37
VLD2012-114
Optimal Design and Performance Evaluation of Residue Arithmetic Circuits with a Binary Coding of Signed-Digit Number
Takuya Kobayashi, Kazuhiro Motegi, Shugang Wei (Gunma Univ.)
pp. 39 - 44
VLD2012-115
Design and Performance Evaluation of RSA Encryption Processor Using Signed-Digit Number Arithmetic
Junichi Asaoka, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 45 - 50
VLD2012-116
Automatic generation of the Power-Switch Driver Circuit and evaluation in Power-gating design implementation
Makoto Miyauchi, Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 51 - 56
VLD2012-117
Scaling the size of Expressions in Random Testing of Arithmetic Optimization of C Compilers
Eriko Nagai, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 57 - 62
VLD2012-118
Break Even Time Evaluation of Run-Time Power Gating Control by On-chip Leakage Monitor
Kensaku Matsunaga, Masaru Kudo (SIT), Yuya Ohta, Nao Konishi (SIT), Hideharu Amano (KU), Ryuichi Sakamoto, Mitaro Namiki (TUAT), Kimiyoshi Usami (SIT)
pp. 63 - 68
VLD2012-119
Speeding up multiple sections of binary code by hardware accelerator tightly coupled with cpu
Shunsuke Satake (Kwansei Gakuin Univ), Nagisa Ishiura, Shimpei Tamura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ), Hiroyuki Kanbara (ASTEM)
pp. 69 - 73
VLD2012-120
Dynamic Multi-Vth Control Using Body Biasing in Silicon on Thin Buried Oxide (SOTB)
Shinya Ajiro, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 75 - 80
VLD2012-121
An Improved Routing Method using Minimum Cost Flow for Routes with Target Wire Lengths
Kazuo Yamane, Kunihiro Fujiyoshi (TUAT)
pp. 81 - 86
VLD2012-122
The Rohm0.18um Chip Design Trial Using AllianceEDA Tool-set and Cell Library Based on Lambda Rule for Deep-submicron Process
-- Trial of Place and Routing Tools --
Tatsuya Hosokawa, Naohiko Shimizu (Tokai Univ.)
pp. 87 - 92
VLD2012-123
An accelerator with minimal data transferring using ring connections
He Guan, Jun Yao, Yasuhiko Nakashima (NAIST)
pp. 93 - 98
VLD2012-124
Design and Implementation of Prioritized On-chip Network with Priority Inversion Avoidance
Takumi Ishida, Daiki Yamazaki, Masakazu Taniguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 99 - 104
VLD2012-125
FPGA-based Implementation of Sliding-Window Aggregates over Disordered Data Streams
Yasin Oge, Masato Yoshimi (Univ. of Electro-Comm.), Takefumi Miyoshi (e-trees), Hideyuki Kawashima (Univ. of Tsukuba), Hidetsugu Irie, Tsutomu Yoshinaga (Univ. of Electro-Comm.)
pp. 105 - 110
VLD2012-126
Low power packet transfer technique on distributed real-time systems
Yusuke Kumura, Osamu Yoshizumi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
pp. 111 - 116
VLD2012-127
Comparison between single host multi-GPU system with ExpEther and multi host system
Shimpei Nomura, Tetsuya Nakahama (Keio Univ.), Junichi Higuchi, Yuki Hayashi, Takashi Yoshikawa (NEC), Hideharu Amano (Keio Univ.)
pp. 117 - 122
VLD2012-128
Low latency network topology using multiple links at each host
Ryuta Kawano (Keio Univ.), Ikki Fujiwara (NII), Hiroki Matsutani, Hideharu Amano (Keio Univ.), Michihiro Koibuchi (NII)
pp. 123 - 128
VLD2012-129
A design of a line buffer module for image proccessing as a library of a high-level synthesis environment
Naohisa Arakawa, Tomonori Izumi (Ritsumeikan Univ.)
pp. 129 - 134
VLD2012-130
A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs
Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.)
pp. 135 - 140
VLD2012-131
The method for automation of design verification using UML diagram
Daiki Kano (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.)
pp. 141 - 146
VLD2012-132
Implementation of a pupil detection method using an FPGA accelerator and a high-level synthesis tool
Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 147 - 152
VLD2012-133
Implementation of 3-D stencil computation with an FPGA accelerator and a high level synthesis tool
Yoshihiro Nakamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 153 - 158
VLD2012-134
Design and Implementation of High Performance Stencil Computer by using Mesh Connected FPGA Arrays
Ryohei Kobayashi, Shinya Takamaeda-Yamazaki, Kenji Kise (Tokyo Tech)
pp. 159 - 164
VLD2012-135
Implementation and performance evaluation of the accelerator for Lattice Boltzmann method on FPGA cluster
Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 165 - 170
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.