IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 114, Number 507

Dependable Computing

Workshop Date : 2015-03-06 - 2015-03-07 / Issue Date : 2015-02-27

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Table of contents

DC2014-88
A Case for Accelerating Data Structure Sever using FPGA NIC
Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 1 - 6

DC2014-89
Implementation evaluation of in-vehicle encrypted CAN communication and replay attack countermeasure technique
Masashi Nakano, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)
pp. 7 - 12

DC2014-90
A HW/SW Cooperative System Design of Stabilization Processing of Images from Networked Cameras for the Realization of an Automatic Watch System for Safe Navigation
Takeshi Ohkawa (Utsunomiya Univ.), Yohei Matsumoto (Tokyo Marine Univ.), Manabu Inagawa (IDi), Daichi Uetake, Mayu Fusegi, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 13 - 18

DC2014-91
Advice : An application design environment for various parallel processing hardware
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.)
pp. 19 - 24

DC2014-92
A Resource Utilization Aware Method to Improve Throughput on RMT Processor
Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, Nobuyuki Yamasaki (Keio Univ.)
pp. 25 - 30

DC2014-93
Adaptive Error Correcting Code by Priority on RMT Processor
Tsukasa Matsui, Shuma Hagiwara, Keigo Mizotani, Nobuyuki Yamasaki (Keio Univ.)
pp. 31 - 36

DC2014-94
Development of soft macro processor for embedded system
Tomoyuki Sugiyama, Takahiro Sasaki, Toshio Kondo (Mie Univ.)
pp. 37 - 42

DC2014-95
A proposal of placement optimization algorithm by introducing TSV module
Atsushi Murata, Tomohiro Inaba, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC)
pp. 43 - 48

DC2014-96
An Algorithm to Reduce Components of a Gaussian Mixture Model Considering Distribution Shape of Each Component
Naoya Yokoyama, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.)
pp. 49 - 54

DC2014-97
Development of Introductory Learning Material for Embedded Systems using Plarail
Takashi Kawanami, Shunpei Kaji, Daisuke Takago, Ryoko Hayashi (KIT)
pp. 55 - 60

DC2014-98
A Trial Investigation System for Vulnerability on M2M Network
Kiyotaka Atsumi (ka-lab)
pp. 61 - 64

DC2014-99
Prevention Peeping System by coordinating LED Light with Smartphones
Kouhei Sugiyama, Kyosuke Kageyama, Takeshi Kumaki, Takeshi Fujino (Ritsumei Univ.)
pp. 65 - 70

DC2014-100
Power optimization of low-power reconfigurable accelerator CMA-SOTB
Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano (Keio Univ.)
pp. 71 - 76

DC2014-101
Improvements and evaluation of bias circuit control for CMOS analog circuit
Ryohei Hori (Ritsumeikan Univ.), Toshio Kumamoto (OSU), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.)
pp. 77 - 82

DC2014-102
A Study on a Power Efficient Neurochip with Non-Volatile Memory
Jun Tomii, Masaaki Kondo, Hiroshi Nakamura (Univ. Tokyo)
pp. 83 - 88

DC2014-103
Energy Reduction of BTB by focusing on Number of Branches per Cache Line
Hiroki Yamamoto, Ryotaro Kobayashi (TUT), Hajime Shimada (NU)
pp. 89 - 94

DC2014-104
Dynamic Scheduling Algorithm for Automatically Parallelized and Power Reduced Applications on Multicore Systems
Takashi Goto, Kohei Muto, Tomohiro Hirano, Hiroki Mikami (Waseda Univ.), Uichiro Takahashi, Sakae Inoue (Fujitsu), Keiji Kimura, Hironori Kasahara (Waseda Univ.)
pp. 95 - 100

DC2014-105
Real-Time Static Voltage and Frequency Scaling on RMT Processor with Instructions Per Clock Cycle Control
Kenji Yamada, Yusuke Hatori, Shuma Hagiwara, Keigo Mizotani, Masayoshi Takasu, Nobuyuki Yamasaki (Keio Univ.)
pp. 101 - 106

DC2014-106
Study of Cost Reduction Technique for FPGA-based Control Systems by Quantitative Evaluation of Dangerous Failure Ratio
Teppei Hirotsu, Tadanobu Toba (Hitachi)
pp. 119 - 124

DC2014-107
Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication
Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.)
pp. 125 - 130

DC2014-108
File access analysis method by hardware monitoring of disk I/O
Kenji Toda, Kazukuni Kobara (AIST)
pp. 131 - 135

DC2014-109
Speed Up co-Simulation for Verification of Embedded Systems
Hiroaki Nakata, Kenta Morishima, Yasuo Sugure (Hitachi)
pp. 137 - 142

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan