Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2012] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [Japanese] / [English]
VLD2015-38
Scan Segmentation Approach to Magnify Detection Sensitivity for Tiny Hardware Trojan
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST)
pp. 1 - 6
VLD2015-39
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
Masato Tamura, Makoto Ikeda (Univ. of Tokyo)
pp. 7 - 12
VLD2015-40
Background Sequence Generation for Neighborhood Pattern Sensitive Fault Testing in Random Access Memories
Shin'ya Ueoka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)
pp. 19 - 24
VLD2015-41
A study on multiple path selection conditions in delay testing using design-for-testability circuit
Mori Ryosuke, Yotsuyanagi Hiroyuki, Hashizume Masaki (Tokushima Univ.)
pp. 25 - 30
VLD2015-42
On discrimination method of a resistive open using delay variation induced by signal transitions on adjacent lines
Kotaro Ise, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 31 - 36
VLD2015-43
Fast Monte Carlo based timing yield calculation
Hiromitsu Awano, Takashi Sato (Kyoto Univ.)
pp. 37 - 42
VLD2015-44
[Fellow Memorial Lecture]
Improving System Dependability by VLSI Test Technology
Seiji Kajihara (KIT)
pp. 43 - 44
VLD2015-45
Improved Method of Simulated Annealing for Unreachable Solution Space
Hiroyuki Nakano, Kunihiro Fujiyoshi (TUAT)
pp. 45 - 50
VLD2015-46
On applications of Monte-Carlo tree search algorithm for CAD problems
Yusuke Matsunaga (Kyushu Univ.)
pp. 51 - 55
VLD2015-47
A Study on DVFS for Heterogeneous Task Set
Mineo Kaneko (JAIST)
pp. 63 - 68
VLD2015-48
[Invited Talk]
Towards Getting Your Paper Accepted at International Conferences
-- Based on Experiences of Studying Abroad and Serving as a Program Committee Member --
Yuko Hara-Azumi (Tokyo Tech)
p. 69
VLD2015-49
[Invited Talk]
Taipei Report
Yasuhiro Takashima (Univ. of Kitakyushu)
p. 71
VLD2015-50
[Invited Talk]
EDA Research Activities in The University of Texas at Austin
Tetsuaki Matsunawa (Toshiba)
p. 73
VLD2015-51
Formulation to SAT for Acceleration in 1D Layout Area Minimization of CMOS circuits
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
pp. 81 - 86
VLD2015-52
Layout Decomposition into L-Shaped Parts for Variable Shaped-Beam Mask Writer
Katsuya Hoshi, Kunihiro Fujiyoshi (TUAT)
pp. 87 - 92
VLD2015-53
Effective Routing Pattern Generation with an Optimum Tertiary Routing Algorithm for Self-Aligned Quadruple Patterning
Takeshi Ihara, Atsushi Takahashi (Tokyo Tech)
pp. 93 - 98
VLD2015-54
A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs
Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 99 - 104
VLD2015-55
An FPGA implementation of real-time position and pose measurement for robotic head
Masahiro Matsumoto, Kazuhiro Shimonomura (Ritsumeikan)
pp. 117 - 121
VLD2015-56
A low-power soft error tolerant latch scheme on 15nm process
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa (Waseda Univ.)
pp. 123 - 127
VLD2015-57
Sleep Control Using Virtual Ground Voltage Detection For Fine-Grain Power Gating
Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 129 - 134
VLD2015-58
Hardware Trojan Identification based on Netlist Features using SVM
Kento Hasegawa, Oya Masaru, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 135 - 140
VLD2015-59
A Quantitative Criterion of Gate-Level Netlist Vulnerability
Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 141 - 146
VLD2015-60
A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 147 - 152
VLD2015-61
Extending Distributed Control for High-Level Synthesis beyond Boundaries of Dataflow Graphs
Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 153 - 158
VLD2015-62
An Approach to Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST)
pp. 159 - 164
VLD2015-63
On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT)
pp. 165 - 170
VLD2015-64
Construction and Evaluation of Three-Dimensional Heat Transfer Simulator for LSI Packages
Shougo Watanabe, Takashi Omura, Yuki Kitagawa, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.)
pp. 171 - 176
VLD2015-65
Implementation of Precision Resistance Measurement of TSVs Using Analog Boundary Scan
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
pp. 177 - 182
VLD2015-66
A Data-dependent Approximation-circuit Design using Timing-error Prediction Scheme and its Evaluations on FPGA
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 183 - 188
VLD2015-67
Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI
Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)
pp. 189 - 194
VLD2015-68
Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits
Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.)
pp. 195 - 200
VLD2015-69
An M by N Algorithm Using Multiple Target Test Generation for Static Test Compaction
Yuya Hara, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon University), Masayoshi Yoshimura (Kyoto Sangyo university)
pp. 207 - 212
VLD2015-70
An approach to LFSR/MISR seed generation for delay fault BIST
Daichi Shimazu, Satishi Ohtake (Oita Univ.)
pp. 213 - 218
VLD2015-71
Design of BIST with soft error resilience for testing FPGAs
Hiroki Ueda, Daichi Shimadu, Satoshi Ohtake (Oita univ.)
pp. 219 - 224
VLD2015-72
Easily-testable Carry Select Adder with Online Error Detection Capability
Nobutaka Kito (Chukyo Univ.)
pp. 225 - 230
VLD2015-73
Fast and Accurate Estimation of Execution Cycles for ARM Architecture
Go Sato, Yuki Ando, Hiroaki Takada, Shinya Honda, Yutaka Matsubara (Nagoya Univ)
pp. 231 - 236
VLD2015-74
Exploration of Address Offsets of Basic Blocks for Cache Hit Ratio Improvement
Junya Goto, Nagisa Ishiura (K.G.)
pp. 237 - 241
VLD2015-75
Hash-table and Balanced-tree based FIB Architecture for CCN Routers Reducing Memory Accesses
Kenta Shimazaki (Waseda Univ.), Takashi Aoki, Takahiro Hatano, Takuya Otsuka, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Yong-Jin Park, Nozomu Togawa (Waseda Univ.)
pp. 243 - 248
VLD2015-76
A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 249 - 253
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.