Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2015-111
Tool Support for Verifying Large Scale Hardware Design with Verilog-HDL
Yuta Morimitsu, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Masafumi Kondo, Hisashi Miyazaki (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.), Norihiro Yoshida (Nagoya Univ.)
pp. 1 - 6
VLD2015-112
Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation
Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 7 - 12
VLD2015-113
Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme
Hiroshi Saito (Univ. Aizu), Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
pp. 13 - 18
VLD2015-114
High-Level Synthesis of Embedded Systems Controller from Erlang
Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM)
pp. 19 - 24
VLD2015-115
A Multi-Paradigm High-Level Hardware Design Environment
Shinya Takamaeda (NAIST)
pp. 25 - 30
VLD2015-116
ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components
Junghoon Oh, Mineo Kaneko (JAIST)
pp. 31 - 36
VLD2015-117
A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis
Keisuke Inoue (KTC), Mineo Kaneko (JAIST)
pp. 37 - 42
VLD2015-118
A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.)
pp. 43 - 48
VLD2015-119
A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation
Hiroki Takaguchi, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.)
pp. 49 - 54
VLD2015-120
Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors
Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 55 - 60
VLD2015-121
Electromagnetic Analysis Attack for Simeck and Simon
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 61 - 66
VLD2015-122
Power Analysis Attack for Countermeasure with Check Circuit
Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ.)
pp. 67 - 72
VLD2015-123
Timing-error-tolerant AES Cipher
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 73 - 78
VLD2015-124
In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 79 - 84
VLD2015-125
[Invited Talk]
VLSI Technology for Embedded Systems in the More than Moore Era
-- Focusing on Leading Edge Medical Applications --
Masaharu Imai, Yoshinori Takeuchi (Osaka Univ.)
p. 85
VLD2015-126
IP Design using High-Level Synthesis Design Flow
Masato Tatsuoka, Ken Imanishi, Hidenori Nakaishi, Takeshi Toyoyama (SNI)
pp. 87 - 92
VLD2015-127
FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis
Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 93 - 98
VLD2015-128
Noise reduction effect for input dependence of Zigzag Power Gating
Tadahiro Kanamoto, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 99 - 103
VLD2015-129
Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX.
Hanano Suzuki, Kimiyoshi Usami (Shibaura IT)
pp. 105 - 110
VLD2015-130
Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control
Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT)
pp. 111 - 116
VLD2015-131
[Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.)
p. 117
VLD2015-132
FPGA Design and Evaluation of Volume Rendering Circuits Using Selector Logic
Keita Igarashi, Masao Yanagisawa, Togawa Nozomu (Waseda Univ.)
pp. 119 - 124
VLD2015-133
An FPGA Implementation of Fast 2D-Ising-Model Solver for the Max-Cut Problem
Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)
pp. 125 - 130
VLD2015-134
A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture
Takahisa Kurose, Hiroki Nakahara, Tetsuo Morimoto (Ehime Univ.)
pp. 131 - 136
VLD2015-135
Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech)
pp. 137 - 142
VLD2015-136
Lithography Hotspot Detection Using Histogram of Oriented Light Propagation
Yoichi Tomioka (UoA), Tetsuaki Matsunawa (Toshiba)
pp. 143 - 148
VLD2015-137
Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA
Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu)
pp. 149 - 154
VLD2015-138
An Algorithm for Reducing Components of a Gaussian Mixture Model 1
-- A Partitioning Method of Components --
Naoya Yokoyama, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.)
pp. 155 - 160
VLD2015-139
An Algorithm for Reducing Components of a Gaussian Mixture Model 2
-- A Method for Calculating Sensitivities --
Daiki Azuma, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.), Takashi Kambe (Kinki Univ.)
pp. 161 - 166
VLD2015-140
Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection
Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech)
pp. 167 - 172
VLD2015-141
Resource Binding in Datapath Synthesis for Performance Enhancement by Post-Silicon Skew Tuning
Kazuho Katsumata, Mineo Kaneko (JAIST)
pp. 173 - 178
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.