Online edition: ISSN 2432-6380
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VLD2023-30
N/A
Kota Hisafuru, Nozomu Togawa (Waseda Univ.)
pp. 1 - 6
VLD2023-31
Loop optimization method for machine learning model in hardware-Trojan Detection
Ryotaro Negishi, Nozomu Togawa (Waseda Univ.)
pp. 7 - 12
VLD2023-32
(See Japanese page.)
pp. 13 - 18
VLD2023-33
Frequency Dependence of Soft Error Rates Induced by Alpha-Particle and Heavy Ion
Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 19 - 24
VLD2023-34
Data Pattern Dependence of the Total Ionizing Dose Effect in Floating-gate and Charge-trap TLC NAND flash memories
Taiki Ozawa, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 25 - 30
VLD2023-35
Evaluation of SEU Sensitivity by Alpha-Particle on PMOS and NMOS Transistors in a 65 nm bulk Process
Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 31 - 36
VLD2023-36
(See Japanese page.)
pp. 37 - 42
VLD2023-37
N/A
Soma Kawakami (Waseda Univ.), Kentaro Ohno, Dema Ba, Satoshi Yagi, Junji Teramoto (NTT), Nozomu Togawa (Waseda Univ.)
pp. 43 - 48
VLD2023-38
Error Correction Decoder of the Surface Code designed in a 22-nm Bulk Process for Fault Torelant Quantum Computers
Ren Aoyama (KIT), Junichiro Kadomoto (UTokyo), Kazutoshi Kobayashi (KIT)
pp. 49 - 53
VLD2023-39
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application
Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo)
pp. 54 - 59
VLD2023-40
Co-design of Strong Lottery Ticket Hypothesis and FeFET-based CiM
Kenshin Yamauchi, Ayumu Yamada, Naoko Misawa, Seong-Kun Cho, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
pp. 60 - 63
VLD2023-41
*
Itsuki Akeno, Hiro Yamazaki, Tetsuya Asai, Kota Ando (Hokkaido Univ)
pp. 64 - 69
VLD2023-42
Preliminary Data-Pattern Analysis towards Energy-Efficient Adaptive In-Cache Computing for CNN Accelerations
Zhengpan Fei, Koji Inoue (Kyushu Univ.)
pp. 70 - 75
VLD2023-43
Leakage-current Based Charge Accumulating Aging Sensor Circuit and Evaluation of NBTI Using Fabricated Chips
Mina Fukushima, Songxiang Wang, Kaito Nagai, Kimiyoshi Usami (SIT)
pp. 76 - 81
VLD2023-44
MTJ-PUF with Input Decoder and Evaluation of Machine Learning Resistance
Takumi Kikuchi, Kimiyoshi Usami (SIT)
pp. 82 - 87
VLD2023-45
Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control
Kousei Kaizu, Kimiyoshi Usami (SIT)
pp. 88 - 93
VLD2023-46
Computation-in-Memory Generating Approximate Random Weight for Neuromorphic Computing
Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
pp. 94 - 95
VLD2023-47
Quantization Method of Computation-in-Memory for 1/10 Memory Size Vision Transformer
Naoko Misawa, Ryuhei Yamaguchi, Ayumu Yamada, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
pp. 96 - 98
VLD2023-48
Design and Error-tolerance of FeFET-based CiM for Hyperdimensional Computing
Chihiro Matsui, Eitaro Kobayashi, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi (Univ. of Tokyo)
pp. 99 - 100
VLD2023-49
Tamper Resistance Evaluation on FPGA for Low-Latency Cipher Sonic
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)
pp. 101 - 105
VLD2023-50
(See Japanese page.)
pp. 106 - 111
VLD2023-51
Implementation of Neural Networks in Memory-based Reconfigurable Processor
Kenta Sasagawa, Tatsuya Nishikawa, Xihong Zhou, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ.)
pp. 112 - 116
VLD2023-52
(See Japanese page.)
pp. 117 - 118
VLD2023-53
A Proposal for Acceleration of FPGA-based Linear Equation Solver using Speculative Execution System
Naoki Kakine, Shuto Yuya, Atsushi Kubota, Tetsuo Hironaka (HCU)
pp. 119 - 124
VLD2023-54
Hardware obfuscation method using Obfuscator-LLVM and Bambu
Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.)
pp. 125 - 130
VLD2023-55
Calculation of Isomorphic/Similar Topology using Graph Theory
Yuto Moriguchi, Nobukazu Takai (KIT)
pp. 131 - 135
VLD2023-56
A multi bit PWM-DAC with calibration for quantum computing
Shunsuke Akahosh, Nobukazu Takai (KIT)
pp. 136 - 139
VLD2023-57
Wearable Perspiration Meter System with 0.18 µm BCD Process and Experimental Investigations for High Precision
Shunsaku Mineo, Ayumu Yamamoto (Shinshu Univ.), Shin-Ichiro Kuroki (Hiroshima Univ.), Hideya Momose (SKINOS), Koh Johguchi (Shinshu Univ.)
pp. 140 - 145
VLD2023-58
Proposed power supply layout for RF circuits with a power panel containing MOM capacitors, bias control lines, and electrostatic protection diodes
Shunto Nishiura, Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
pp. 146 - 149
VLD2023-59
WGAN-GP based AI accelerator fault detection and fault classification analysis
Shuming Xu, Kazuteru Namba (Chiba Univ.)
pp. 150 - 155
VLD2023-60
On Reducing Area Overhead of BIST for Approximate Multiplier Considering Truncated Bits
Daichi Akamatsu, Shougo Tokai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 156 - 161
VLD2023-61
Implementation Evaluation of a Memorism Pattern Matching Accelerator on FPGA
Shion Honda, Tatsuya Nishikawa, Xihong Zhou, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Katsumi Inoue (AOT)
pp. 162 - 167
VLD2023-62
Takumi Sugioka, Yosikazu Nagamura (Tokyo Metoropolitan Univ.), Masayuki Arai (Nihon Univ.), Satoshi Fukumoto (Tokyo Metoropolitan Univ.)
pp. 168 - 172
VLD2023-63
Backside Side-Channel Attack by Silicon Substrate Voltage and Simulation
Rikuu Hasegawa, Kazuki Monta, Takuya Watatsumi, Takuji Miki, Makoto Nagata (Kobe Univ)
pp. 173 - 177
VLD2023-64
Derivation of secret keys by differential fault analysis using backside voltage fault injection
Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.)
pp. 178 - 181
VLD2023-65
Analysis for S-parameter differences caused by differences in ground definitions for electromagnetic simulations in high-frequency differential GSSG PADs
Ryotaro Sugimoto, Satoshi Tanaka, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.)
pp. 182 - 186
VLD2023-66
Study on the Application of Compressed Sensing Utilizing Random Undersampling to Heart Sound Measurement System
Tomoya Yamamoto, Daisuke Kanemoto, Hirotada Masuda, Tetsuya Hirose (Osaka Univ)
pp. 187 - 191
VLD2023-67
A comparator with variable offset voltage variation by controlling differential pair’s currents
Taira Sakaguchi, Satoshi Komatsu (Tokyo Denki Univ.)
pp. 192 - 197
VLD2023-68
CiM-based Low-bit Neural Network Accelerator Design Method with automatic I/O range optimization
Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo)
pp. 198 - 199
VLD2023-69
Low-Latency Hardware Implementation for SPHINCS+ signature generation
Yuta Takeshima, Makoto Ikeda (The Univ. of Tokyo)
pp. 200 - 204
VLD2023-70
A wafer-scale VLSI realization using optical reconfiguration architecture
Atsushi Takata, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 205 - 208
VLD2023-71
Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory
Sae Goto, Minoru Watanabe (Okayama Univ.), Akifumi Ogiwara (Kobe City College of Technology), Nobuya Watanabe (Okayama Univ.)
pp. 209 - 214
VLD2023-72
Configuration Data Compression for SLM Fine-grained Reconfigurable Logic
Souhei Takagi, Takuya Kozima, Hideharu Amano (Keio Univ), Morihiro Kuga, Masahiro Iida (Kumamoto Univ)
pp. 215 - 220
VLD2023-73
Hardware Compression Method Applying Bernoulli Approximation for Bayesian Neural Networks
Taisei Saito, Kota Ando, Tetsuya Asai (Hokkaido Univ.)
pp. 221 - 226
VLD2023-74
Maximum operating clock frequency evaluation of Mono Instruction Set Computers on an optically reconfigurable gate array VLSI
Soma Imai, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 227 - 230
VLD2023-75
High-Level Synthesis Implementation of a Reservoir Computing based on Chaotic Boltzmann Machine
-- Improving scalability and efficiency of sparse matrix multiplication through a dedicated data compression in external memory --
Shigeki Matsumoto, Yuki Ichikawa, Nobuki Kajihara (IVIS), Hakaru Tamukoh (kyutech)
pp. 231 - 236
VLD2023-76
Study of High-Performance FOC Motor Control using FPGA Processing
Ludi Wang, Takeshi Ohkawa (Kumamoto Univ)
pp. 237 - 242
VLD2023-77
An Improved Routing Method by SAT for Set-Pair Routing Problem
Koki Nagakura, Kunihiro Fujiyoshi (TUAT)
pp. 243 - 248
VLD2023-78
Evaluation of the power consumption of the codec chip EG2C for a visual prosthesis
Shogo Hirayama, Naoya Tanaka, Yoshinori Takeuchi (Kindai Univ.)
pp. 249 - 254
VLD2023-79
(See Japanese page.)
pp. 255 - 260
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.