Online edition: ISSN 2432-6380
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VLD2024-27
[Keynote Address]
Development of AI-oriented processors in Preferred Networks
Jun Makino (PFN/Kobe U.)
pp. 1 - 7
VLD2024-28
Low-bit Quantization Methods for Neural Networks
Emi Wada, Shinji Kimuda (Waseda Univ.)
pp. 8 - 13
VLD2024-29
Efficient inference method using adaptive variable time steps in SNN
Naoya Watanabe, Yoshinori Takeuchi (Kindai)
pp. 14 - 19
VLD2024-30
New Cluster Architecture and Clustering Method Using PAE Cells for eFPGA IP
Ryo Iwasaki, Tatsuya Sasaki, Kenshu Seto, Masahiro Iida (Kumamoto Univ)
pp. 20 - 25
VLD2024-31
Power Reduction Technique for Low Noise Amplifier in Random Undersampling Compressed Sensing EEG Measurement System
Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ.)
pp. 26 - 31
VLD2024-32
Low Power ΔΣ Modulator With Low Voltage OTA for Wearable Application
Naoya Maruyama, Satoshi Komatsu (Tokyo Denki Univ.)
pp. 32 - 36
VLD2024-33
Design of a Low-Energy MTJ-Based Nonvolatile Register Based on Differential Information Storing Scheme
Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu (Tohoku Uviv.)
pp. 37 - 42
VLD2024-34
FPGA Implementation of Multiplication-Free Table-Lookup-Based CNN Accelerator
Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki (AIST)
pp. 43 - 48
VLD2024-35
Evaluation of Techniques for Ultra-Long Bit-Width Floating-Point Arithmetic on FPGAs
Shintaro Kawasaki, Kuwazawa Gen, Yoshiki Yamaguchi (Univ. Tsukuba)
pp. 49 - 54
VLD2024-36
Implementation and Evaluation of Arithmetic Masking to Mitigate Side-channel Attacks on Wavefront Array-based DNN Accelerator
Hirokatsu Yamasaki, Kota Yoshida, Yuta Fukuda, Takeshi Fujino (Ritsumeikan Univ)
pp. 55 - 60
VLD2024-37
Accelerating CRS Format Conversion for Sparse Matrix Computation with FPGA
Tomoya Yokono, Yoshiki Ymaguchi (Univ of Tsukuba)
pp. 61 - 66
VLD2024-38
On Reducing Area Overhead of Pseudo-Random Pattern Generator in BIST for Approximate Multiplier
Daichi Akamatsu, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ)
pp. 67 - 72
VLD2024-39
On design of a delay testable circuit with an embedded arbiter PUF
Hayato Miki, Hiroyuki Yotsuyanagi (Tokushima Univ.), Masaki Hashizume (OUJ)
pp. 73 - 78
VLD2024-40
Design of SNU-tolerant non-volatile Flip-Flop
Kyotaro Takahashi, Kazuteru Namba (Chiba Univ.)
pp. 79 - 83
VLD2024-41
Evaluating Soft Error Tolerance and Proposing an Error Detection Method for TFHE Applications Running on GPUs (*)
Masakazu Yoshida, Kotaro Matsuoka, Masanori Hashimoto (Kyoto Univ.)
pp. 84 - 88
VLD2024-42
Utilization of Signal Similarity in Compressed Sensing
-- Realizing Low-power Dissipation Wireless EEG Monitoring Circuit System --
Daisuke Kanemoto, Eichi Takimoto, Tetsuya Hirose (Osaka Univ.)
pp. 89 - 94
VLD2024-43
Application of Simulated Annealing to Wireless EEG Measurement in Compressed Sensing
Shodai Motomochi, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ)
pp. 95 - 99
VLD2024-44
Development of a Random Undersampling SARADC in a Wireless EEG Measurement System Utilizing Compressed Sensing
Takuma Matsumoto, Daisuke Kanemoto, Wataru Okumura, Riku Matsubara, Tetsuya Hirose (Osaka Univ)
pp. 100 - 104
VLD2024-45
LDO sizing using Bayesian optimization handling PVT corner and requirement
Tsuyoshi Masubuchi (GU), Nobukazu Takai (KIT)
pp. 105 - 108
VLD2024-46
Comparison of Analog Circuit Sizing Performance in Bayesian Optimization using Algorithms for Higher Dimensions
Ryo Takagi (KIT), Tsuyoshi Masubuchi (Gunma Univ.), Yuto Moriguchi, Nobukazu Takai (KIT)
pp. 109 - 113
VLD2024-47
Enhancing the Efficiency of Analog Integrated Circuits using by Explainable AI
Takayoshi Namura, Yuto Moriguchi, Nobukazu Takai (KIT)
pp. 114 - 119
VLD2024-48
Study on a Scalable Chopper-Stabilized Auto-Zero Amplifier for Wireless EEG Measurement
Yukito Yoshikawa, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ)
pp. 120 - 125
VLD2024-49
Validation of a design methodology for security systems utilizing compressed sensing and chain-generated noise masking.
Tomoya Yamamoto, Daisuke Kanemoto, Ryota Tsunaga, Tetsuya Hirose (Osaka Univ)
pp. 126 - 130
VLD2024-50
Temperature sensor with Time-to-Digital Converter for low-voltage operation
Kaito Nagai, Kimiyoshi Usami (SIT)
pp. 131 - 136
VLD2024-51
Prametric Yield Estimation using Bayesian Neural Networks
Yuto Moriguchi, Nobukazu Takai (KIT)
pp. 137 - 141
VLD2024-52
Digital Circuit Topology Search Using Genetic Algorithm with Block Structure
Hikaru Horikawa, Nobukazu Takai (KIT)
pp. 142 - 146
VLD2024-53
Implementarion of Multi-Channel Fast Audio Convolution on FPGA
Masatsugu Okazaki (Yamaha), Ryuji Kawashima, Ryosuke Takagi (YHD)
pp. 147 - 152
VLD2024-54
A Preliminary Evaluation of fDTM-PUF with TDC Sensor for Controlled Threshold
Kazuki Fujimoto, Yuta Fukuda, Tatsuya Oyama (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Takeshi Fujino (Ritsumeikan Univ.)
pp. 153 - 158
VLD2024-55
A Low-Cost Point Cloud Deep Learning Model Using Neural ODE for FPGAs
Mizuki Yasuda, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.)
pp. 159 - 164
VLD2024-56
(See Japanese page.)
pp. 165 - 170
VLD2024-57
Ryusei Eda, Nozomu Togawa (Waseda Univ.)
pp. 171 - 176
VLD2024-58
Cryogenic Transistor Current Modeling Based on Sparse Gaussian Process Regression
Tetsuro Iwasaki (KIT), Takashi Sato (KU), Michihiro Shintani (KIT)
pp. 177 - 182
VLD2024-59
Development of generative AI-based automated design technology for AI chips
Yasutaka Serizawa, Hisanori Matsumoto (Hitachi)
pp. 183 - 187
VLD2024-60
A development of Adaptive Bias Attachment for Low-Power Analog Circuit Design
Shunsuke Akahoshi, Nobukazu Takai (KIT)
pp. 188 - 192
VLD2024-61
Effects of Input Signal Power on Nonlinear Amplifiers in Semantic Communication
Qijian Zhang, Daisuke Umehara, Nobukazu Takai (KIT)
pp. 193 - 197
VLD2024-62
Implementation and Performance Evaluation of an FPGA-Based Electronic Circuit Simulator with a Speculative Execution Linear Solver using Gauss-Jordan Elimination and the BiCGSTAB Method
Yuya Shuto, Yuma Omoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 198 - 203
VLD2024-63
Proposal for NV of Logic Cell Architecture for eFPGA IP
Keizo Hiraga (SSS), Kensu Seto, Masahiro Iida (Kumamoto Univ), Kazuhiro Bessho (SSS)
pp. 204 - 209
VLD2024-64
"Enhancing VPN Gateway Performance through Reconfigurable Hardware Acceleration
Kenji Tanaka, Naoki Miura, Takeshi Sakamoto (NTT)
pp. 210 - 215
VLD2024-65
LSI Design and Tape-Out Case Studies Using Open-Source EDA
Masakazu Hioki, Toshihiro Katashita, Yohei Hori, Hiroshi Fuketa, Ippei Akita (AIST)
pp. 216 - 219
VLD2024-66
A Study on the Validity of Logic Synthesis Result Selection with Imposed Design Constraints
Masashi Imai (Hirosaki Univ.)
pp. 220 - 225
VLD2024-67
Student lab. for entry of the semiconductor education with Agile-chip platform
Hideharu Amano, Atsushi Kosuge, Naonobu Shimamoto, Toru Mogami, Yukinori Ochiai, Hirofumi Sumi, Yurie Inoue, Makoto Ikeda, Yoshio Mita (U. Tokyo)
pp. 226 - 231
VLD2024-68
An Evaluation of Lightweight Hash for Message Authentication Code in CMOS Image Sensors
Manami Hagizaki, Hiroaki Ogawa, Oyama Tatsuya, Takeshi Fujino, Okura Shunsuke (Ritsumeikan Univ.)
pp. 232 - 237
VLD2024-69
On-chip contact angle sensor using coplanar capacitors
Hayato Fukui, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture)
pp. 238 - 242
VLD2024-70
Impact of Size Effect on Delay Time of On-Chip Interconnects under Cryogenic Conditions
Tatsuya Ueda, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ Shiga Prefecture)
pp. 243 - 246
VLD2024-71
[Invited Talk]
Annual Report of A Start-Up Community for Open-Source Silicon in Japan.
Noritsuna Imamura (ISHI-Kai), Akira Tsuchiya (The University of Shiga Prefecture), Takeshi Kuboki (Kumamoto Univ.), Mizuki Mori (Keio Univ.)
pp. 247 - 252
VLD2024-72
(See Japanese page.)
pp. 253 - 258
VLD2024-73
(See Japanese page.)
pp. 259 - 264
VLD2024-75
(See Japanese page.)
pp. 271 - 276
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.