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Technical Committee on Silicon Device and Materials (SDM) (Searched in: 2009)
Search Results: Keywords 'from:2010-02-05 to:2010-02-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| SDM | 2010-02-05 10:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Keynote Address]
Key Issues and Future Prospects for 3-D Integration Technology Mitsumasa Koyanagi, Takafumi Fukushima, Kangwook Lee, Tetsu Tanaka (Tohoku Univ.)  SDM2009-182 |
[more] | SDM2009-182 pp.1-6 |
| SDM | 2010-02-05 10:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Highly-Reliable Cu Interconnect covered with CoWB Metal-cap in a Waterproof Molecular-Pore-Stack (MPS)-SiOCH film Yoshihiro Hayashi, Masayoshi Tagami, Naoya Furutake, Naoya Inoue, Emiko Nakazawa, Kouji Arita (NEC Electronics) SDM2009-183 |
A new low-power copper (Cu) interconnect structure is developed with selective-metal (CoWB) cap, which selectively cover... [more] | SDM2009-183 pp.7-11 |
| SDM | 2010-02-05 11:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Feasibility Study of 70nm Pitch Cu/Porous Low-k D/D Integration Featuring EUV Lithography toward 22nm Generation Naofumi Nakamura, Noriaki Oda, Eiichi Soda, Nobuki Hosoi, Akifumi Gawase, Hajime Aoyama, Y. Tanaka, D. Kawamura, S. Chikaki, M. Shiohara, Nobuaki Tarumi, S. Kondo, Ichiro Mori, S. Saito (SELETE) SDM2009-184 |
A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru... [more] | SDM2009-184 pp.13-18 |
| SDM | 2010-02-05 13:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Advanced Direct-CMP Process for Porous Low-k Thin Film Hayato Korogi (Panasonic), Hiroyuki Chibahara (Renesas), S. Suzuki, M. Tsutsue (Panasonic), K. Seo (Panasonic Semiconductor Engineering), Y. Oka, K. Goto, M. Akazaw, Hiroshi Miyatake (Renesas), S. Matsumoto, T. Ueda (Panasonic) SDM2009-185 |
In order to reduce the effective dielectric constant (keff) for the 32 nm technology node and beyond, Direct-CMP of a po... [more] | SDM2009-185 pp.19-23 |
| SDM | 2010-02-05 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Optimization of Metallization Processes for 32-nm node Highly Reliable Ultralow-k (k=2.4)/Cu Multilevel Interconnects Incorporating a Bilayer Low-k Barrier Cap (k=3.9) M. Iguchi, S. Yokogawa, Hirokazu Aizawa, Y. Kakuhara, Hideaki Tsuchiya, Norio Okada, Kiyotaka Imai, M. Tohara, K. Fujii (NEC Electronics), T. Watanabe (Toshiba) SDM2009-186 |
Reliability of 32-nm-node ultralow-k (k=2.4)/Cu multilevel interconnects incorporating a bilayer low-k barrier cap (k=3.... [more] | SDM2009-186 pp.25-29 |
| SDM | 2010-02-05 14:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond Yumi Hayashi, Noriaki Matsunaga, Makoto Wada, Shinichi Nakao, Atsuko Sakata, Kei Watanabe, Hideki Shibata (Toshiba) SDM2009-187 |
Silicide-cap for Cu interconnects is promising for enhancing electromigration (EM) performance for 32 nm-node and beyond... [more] | SDM2009-187 pp.31-36 |
| SDM | 2010-02-05 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Performance of Cu Dual-Damascene Interconnects Using a Thin Ti-Based Self-Formed Barrier Layer for 28-nm Node and Beyond K. Ohmori, K. Mori, K. Maekawa (Renesas), Kazuyuki Kohama, Kazuhiro Ito (Kyoto Univ.), T. Ohnishi, M. Mizuno (KOBE STEEL), K. Asai (Renesas), M. Murakami (Ritsumeikan Trust), Hiroshi Miyatake (Renesas) SDM2009-188 |
With continuous shrinkage of advanced ULSIs, the impact of line resistance on the devices has become more and more serio... [more] | SDM2009-188 pp.37-41 |
| SDM | 2010-02-05 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Chip-Level and Package-Level Seamless Interconnect Technologies for Advanced Packaging Shintaro Yamamichi, Kentaro Mori, Katsumi Kikuchi, Hideya Murai, D. Ohshima, Y. Nakashima (NEC), Kouji Soejima, Masaya Kawano (NEC Electronics), Tomoo Murakami (NEC) SDM2009-189 |
Interposer-process-oriented thick-Cu-wiring technologies have been developed. Cu wiring thickness is 5 to 10 um, and int... [more] | SDM2009-189 pp.43-48 |
| SDM | 2010-02-05 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Defects in Cu/low-k Interconnects Probed Using Monoenergetic Positron Beams Akira Uedono (Tsukuba Univ.), Naoya Inoue, Y. Hayashi, K. Eguchi, T. Nakamura, Y. Hirose, Masaki Yoshimaru (STARC), Nagayasu Oshima, Toshiyuki Ohdaira, R. Suzuki (National Institute of Advanced Industrial Science and Technology) SDM2009-190 |
Defects in SiOCH/Cu damascene structures were probed using monoenergetic positron beams. Doppler broadening spectra of t... [more] | SDM2009-190 pp.49-52 |
| SDM | 2010-02-05 16:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Evaluation of Dielectric Constant through Direct CMP of Porous Low-k Film Masako Kodera, T. Takahashi, G. Mimamihaba (Toshiba Corp.) SDM2009-191 |
Nanoporous materials are utilized in current devices. However, their low-k value often alters during device fabrication.... [more] | SDM2009-191 pp.53-58 |
| SDM | 2010-02-05 16:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Evaluation of Line-Edge Roughness in Cu/Low-k Interconnect Patterns Atsuko Yamaguchi, D. Ryuzaki, Kenichi Takeda (Hitachi), Hiroki Kawada (Hitachi High-Tech.) SDM2009-192 |
To establish the method for evaluating Cu/low-k interconnect line-edge roughness (LER), resist, low-k, and Cu/low-k samp... [more] | SDM2009-192 pp.59-63 |
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