Conference Date	Wed, Jan 25, 2012 10:00 - 18:00 Thu, Jan 26, 2012 09:00 - 17:05
Topics	FPGA Applications, etc
Conference Place	Hiyoshi Campus, Keio University
Address	4-1-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8521, Japan
Transportation Guide	http://www.keio.ac.jp/ja/access/hiyoshi.html
Contact Person	Prof. Hideharu Hamano 045-560-1064
Announcement	We will have a party on Jan. 25th. Fee is 5,000Yen for non-students, and 3,000Yen for Student. If you want to join the party, please send an e- to vld-party1201vlsiest using the form in the Japanese page.
Copyright and reproduction	All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Wed, Jan 25 AM  FPGA Applications Chair: Atsushi Takahashi (Osaka Univ.) 10:00 - 12:05
(1) VLD	10:00-10:25	Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications VLD2011-91 CPSY2011-54 RECONF2011-50	Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(2) VLD	10:25-10:50	Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register VLD2011-92 CPSY2011-55 RECONF2011-51	Keita Manabe, Rika Uegaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(3) VLD	10:50-11:15	Sound preprocessing circuit by consonant and vowel recognition system VLD2011-93 CPSY2011-56 RECONF2011-52	Keita Okamoto, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(4) VLD	11:15-11:40	Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift VLD2011-94 CPSY2011-57 RECONF2011-53	Takatosi Uchizono, Kazuya Osaku, Akinobu Tsuyuki, Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa (TUAT)
(5) VLD	11:40-12:05	An Image Recognition System with Hierarchical Feature Learning Function VLD2011-95 CPSY2011-58 RECONF2011-54	Masahiro Ariizumi, Baku Ogasawara, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
Wed, Jan 25 PM  Reconfigurable and Real time Processing Chair: Takeshi Takenaka (NEC) 13:30 - 14:45
(6) RECONF	13:30-13:55	On a Decomposed MTMDDs for CF Machine VLD2011-96 CPSY2011-59 RECONF2011-55	Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT)
(7) CPSY	13:55-14:20	An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor VLD2011-97 CPSY2011-60 RECONF2011-56	Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ)
(8) CPSY	14:20-14:45	Extension of ITRON Specification OS for Multithreaded Processors VLD2011-98 CPSY2011-61 RECONF2011-57	Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
Wed, Jan 25 PM  Network Applications Chair: Nobuki Kajiwara (Renesas Electronics) 14:55 - 16:10
(1) CPSY	14:55-15:20	Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router VLD2011-99 CPSY2011-62 RECONF2011-58	Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.)
(2) RECONF	15:20-15:45	A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique VLD2011-100 CPSY2011-63 RECONF2011-59	Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba)
(3) CPSY	15:45-16:10	A bandwidth control scheme based on a traffic analysis for an on-chip router VLD2011-101 CPSY2011-64 RECONF2011-60	Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.)
Wed, Jan 25 PM  Dynamically Reconfigurable Computing and Robots Chair: Akihisa Yamada (Sharp) 16:20 - 18:00
(4) RECONF	16:20-16:45	A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP VLD2011-102 CPSY2011-65 RECONF2011-61	Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.)
(5) RECONF	16:45-17:10	Architecture and estimation of reconfigurable processor for multimedia processing VLD2011-103 CPSY2011-66 RECONF2011-62	Asuka Hayashi, Shuu'ichirou Yamamoto, Hideo Maejima (Tokyo Tech)
(6) VLD	17:10-17:35	Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit VLD2011-104 CPSY2011-67 RECONF2011-63	Yusaku Yamazaki, Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(7) VLD	17:35-18:00	A Mobile Robot System using Intelligent Circuit in Silicon VLD2011-105 CPSY2011-68 RECONF2011-64	Takuya Suzuki, Yusaku Yamazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
Thu, Jan 26 AM  Hi-level Synthesis and Arithmetic Applications(1) Chair: Hiroki Matsutani (Keio Univ.) 09:00 - 10:15
(8) VLD	09:00-09:25	Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation VLD2011-106 CPSY2011-69 RECONF2011-65	Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
(9) VLD	09:25-09:50	High-Level Synthesis of Hardware Relinkable to Software VLD2011-107 CPSY2011-70 RECONF2011-66	Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO)
(10) RECONF	09:50-10:15	The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams VLD2011-108 CPSY2011-71 RECONF2011-67	Daiki Kano, Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH)
Thu, Jan 26 AM  Hi-level Synthesis and Arithmetic Applications(2) Chair: Hiroyuki Tomiyama (Ritsumeikan Univ.) 10:25 - 11:40
(11) VLD	10:25-10:50	Interconnect Reduction in Binding Procedure of HLS VLD2011-109 CPSY2011-72 RECONF2011-68	Hao Cong, Song Chen, Takeshi Yoshimura (Waseda Univ.)
(12) VLD	10:50-11:15	A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set VLD2011-110 CPSY2011-73 RECONF2011-69	Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(13) VLD	11:15-11:40	Error Checker using Binary tree structure of Residue Signed-Digit Additions VLD2011-111 CPSY2011-74 RECONF2011-70	Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.)
Thu, Jan 26 PM  GPU and HPC Chair: Hideharu Amano(Keio Univ.) 12:40 - 15:10
(14) CPSY	12:40-13:05	Discussion of Performance Prediction Model for Symmetric Block Ciphers on CUDA VLD2011-112 CPSY2011-75 RECONF2011-71	Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA)
(15) RECONF	13:05-13:30	Fine-grained Adaptive Power Management for Energy Efficient GPU computing	Makoto Murasaki, Tsuyoshi Hamada, Felipe A. Cruz (NACC)
(16) CPSY	13:30-13:55	development and evaluation of ParaRuby: a distributed GPGPU framework using Ruby VLD2011-113 CPSY2011-76 RECONF2011-72	Ryo Nakamura, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.)
(17) CPSY	13:55-14:20	Implementation and its Evaluation of Distributed PC Grid System VLD2011-114 CPSY2011-77 RECONF2011-73	Junji Umemoto, Hiroyuki Ebara, Bunryu U (Kansai Univ.)
(18) VLD	14:20-14:45	Implementation of Numerical Circuit on 3D FPGA-Array VLD2011-115 CPSY2011-78 RECONF2011-74	Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT)
(19) RECONF	14:45-15:10	Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster VLD2011-116 CPSY2011-79 RECONF2011-75	Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.)
Thu, Jan 26 PM  Reconfigurable Devices Chair: Moritoshi Yasunaga (Univ. of Tsukuba) 15:25 - 17:05
(20) RECONF	15:25-15:50	Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device	Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ)
(21) RECONF	15:50-16:15	0.18 um process optically reconfigurable gate array VLSI VLD2011-117 CPSY2011-80 RECONF2011-76	Takahiro Watanabe, Minoru Watanabe (Shizuoka Univ.)
(22) RECONF	16:15-16:40	Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit VLD2011-118 CPSY2011-81 RECONF2011-77	Takashi Yoza, Minoru Watanabe (Shizuoka Univ.)
(23) VLD	16:40-17:05	Study of pattern area and reconfigurable logic circuit with DG/CNT transistor VLD2011-119 CPSY2011-82 RECONF2011-78	Takamichi Hayashi, Shigeyoshi Watanabe (SIT)

Contact Address and Latest Schedule Information
VLD	Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
	Contact Address	Kazutoshi Kobayashi (Kyoto Institute of Technology) E-: bat Tel: +81-75-724-7452
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
CPSY	Technical Committee on Computer Systems (CPSY)   [Latest Schedule]
	Contact Address	Akira ASATO (FUJITSU) TEL +81-44-754-3233, FAX +81-44-754-3214 E-: a
RECONF	Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
	Contact Address	Shorin Kyo (Renesas Electronics Corp.) E-: snkwzs TEL: +81-44-435-5446 FAX: +81-44-435-5432
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
	Contact Address	Nozomu Togawa (Waseda University) Email sldm2011g

Last modified: 2012-01-26 09:33:37